New split bus interface 2 / Verilator simulation support

[flooklab]

Continue #145
Extend sbus support & add modifications to run simulation with Verilator.
The bus can be either fully split (use/add new modules using sbus)
or it can be also only split in the tb module (same old modules, no other changes required).

• Adds simulation driver for split Basil bus.
• Adds split bus tests for GPIO modules (for new "sbus GPIO module" and old "normal bus GPIO module").

To run with Verilator (and get .vcd output) one may currently add
mkfile += "EXTRA_ARGS += -Wno-UNSIGNED -Wno-WIDTH -Wno-WIDTHCONCAT --trace"
to the Makefile

[codecov]

Codecov Report

Merging #146 (34e3e0c) into master (e9542bc) will decrease coverage by 0.46%.
The diff coverage is 0.00%.

@@            Coverage Diff             @@
##           master     #146      +/-   ##
==========================================
- Coverage   32.38%   31.92%   -0.47%     
==========================================
  Files          71       72       +1     
  Lines        4712     4780      +68     
==========================================
  Hits         1526     1526              
- Misses       3186     3254      +68     

Impacted Files	Coverage Δ
basil/utils/sim/BasilBusDriver.py	0.00% <0.00%> (ø)
basil/utils/sim/BasilSbusDriver.py	0.00% <0.00%> (ø)
basil/utils/sim/SiLibUsbBusDriver.py	0.00% <0.00%> (ø)

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[themperek]

Any idea of how we can reduce this repeating code tests/test_SimGpio_xxx.py maybe something like this: https://stackoverflow.com/questions/38729007/parametrize-class-tests-with-pytest#:~:text=From%20the%20docs%3A-,%40pytest.,test%20methods%20in%20the%20class.

[flooklab]

Any idea of how we can reduce this repeating code tests/test_SimGpio_xxx.py maybe something like this: https://stackoverflow.com/questions/38729007/parametrize-class-tests-with-pytest#:~:text=From%20the%20docs%3A-,%40pytest.,test%20methods%20in%20the%20class.

The only line that changes is in the setUp() function. setUp cannot be parametrized like this.
I tried to inherit from the main test and override setUp instead. For some reason this does not work properly yet

[themperek]

Any idea of how we can reduce this repeating code tests/test_SimGpio_xxx.py maybe something like this: https://stackoverflow.com/questions/38729007/parametrize-class-tests-with-pytest#:~:text=From%20the%20docs%3A-,%40pytest.,test%20methods%20in%20the%20class.

The only line that changes is in the setUp() function. setUp cannot be parametrized like this.
I tried to inherit from the main test and override setUp instead. For some reason this does not work properly yet

https://stackoverflow.com/questions/28695276/how-to-parameterize-python-unittest-setup-method ?

[themperek]

may be not needed?

[flooklab]

Yes for sbus it (GPIO test) runs fine without hack with iverilog. For bus not.

[flooklab]

Any idea of how we can reduce this repeating code tests/test_SimGpio_xxx.py maybe something like this: https://stackoverflow.com/questions/38729007/parametrize-class-tests-with-pytest#:~:text=From%20the%20docs%3A-,%40pytest.,test%20methods%20in%20the%20class.

The only line that changes is in the setUp() function. setUp cannot be parametrized like this.
I tried to inherit from the main test and override setUp instead. For some reason this does not work properly yet

https://stackoverflow.com/questions/28695276/how-to-parameterize-python-unittest-setup-method ?

cab7212

[themperek]

Thank you. Let it go in.
Can you squash all these commits to 2-3 that makes sense?
I can alternatively make 1 from GitHub GUI when merging.

[flooklab]

Can you squash all these commits to 2-3 that makes sense?

I can have a look

[flooklab]

Done @themperek

[themperek]

It is suffering. Thank you!