ENH: use preprocessor to switch buses

basil/utils/sim/utils.py

@@ -43,6 +43,13 @@ def cocotb_makefile(sim_files, top_level='tb', test_module='basil.utils.sim.Test
     mkfile += extra
     mkfile += "\n"
 
+    try:
+        if os.environ['SIM'] == 'verilator':
+            mkfile += "EXTRA_ARGS += -DVERILATOR_SIM\n"
+            mkfile += "EXTRA_ARGS += -Wno-WIDTH -Wno-TIMESCALEMOD\n"
+    except KeyError:
+        pass
+
     mkfile += """
 export SIMULATION_HOST
 export SIMULATION_PORT

tests/test_SimGpio.py

@@ -55,13 +55,19 @@
 
 
 class TestSimGpio(unittest.TestCase):
-    def __init__(self, testname, tb='test_SimGpio.v', bus='basil.utils.sim.BasilBusDriver'):
+    def __init__(self, testname, tb='test_SimGpio.v', bus_drv='basil.utils.sim.BasilBusDriver', bus_split=False):
         super(TestSimGpio, self).__init__(testname)
         self._test_tb = tb
-        self._sim_bus = bus
+        self._sim_bus = bus_drv
+        self._bus_split_def = ()
+        if bus_split is not False:
+            if bus_split == 'sbus':
+                self._bus_split_def = ("BASIL_SBUS",)
+            elif bus_split == 'top':
+                self._bus_split_def = ("BASIL_TOPSBUS",)
 
     def setUp(self):
-        cocotb_compile_and_run(sim_files=[os.path.join(os.path.dirname(__file__), self._test_tb)], sim_bus=self._sim_bus)
+        cocotb_compile_and_run(sim_files=[os.path.join(os.path.dirname(__file__), self._test_tb)], sim_bus=self._sim_bus, extra_defines=self._bus_split_def)
 
         self.chip = Dut(cnfg_yaml)
         self.chip.init()

tests/test_SimGpio.v

@@ -7,15 +7,31 @@
 
 `timescale 1ps / 1ps
 
-`include "utils/bus_to_ip.v"
+`ifdef BASIL_SBUS
+    `define SPLIT_BUS
+`elsif BASIL_TOPSBUS
+    `define SPLIT_BUS
+`endif
+
 `include "gpio/gpio_core.v"
-`include "gpio/gpio.v"
+`ifndef BASIL_SBUS
+    `include "utils/bus_to_ip.v"
+    `include "gpio/gpio.v"
+`else
+    `include "utils/sbus_to_ip.v"
+    `include "gpio/gpio_sbus.v"
+`endif
 
 module tb (
     input wire          BUS_CLK,
     input wire          BUS_RST,
     input wire  [15:0]  BUS_ADD,
+`ifndef SPLIT_BUS
     inout wire  [7:0]   BUS_DATA,
+`else
+    input wire  [7:0]   BUS_DATA_IN,
+    output wire [7:0]   BUS_DATA_OUT,
+`endif
     input wire          BUS_RD,
     input wire          BUS_WR
 );
@@ -26,9 +42,29 @@ localparam GPIO_HIGHADDR = 16'h000f;
 localparam GPIO2_BASEADDR = 16'h0010;
 localparam GPIO2_HIGHADDR = 16'h001f;
 
+// Connect tb internal bus to external split bus
+`ifdef BASIL_TOPSBUS
+    wire [7:0] BUS_DATA;
+    assign BUS_DATA = BUS_DATA_IN;
+    assign BUS_DATA_OUT = BUS_DATA;
+`elsif BASIL_SBUS
+    wire [7:0] BUS_DATA_OUT_1;
+    wire [7:0] BUS_DATA_OUT_2;
+    assign BUS_DATA_OUT = BUS_DATA_OUT_1 | BUS_DATA_OUT_2;
+`endif
+
+/* verilator lint_off UNOPT */
 wire [23:0] IO;
 
+assign IO[15:8] = IO[7:0];
+assign IO[23:20] = IO[19:16];
+/* verilator lint_on UNOPT */
+
+`ifndef BASIL_SBUS
 gpio #(
+`else
+gpio_sbus #(
+`endif
     .BASEADDR(GPIO_BASEADDR),
     .HIGHADDR(GPIO_HIGHADDR),
     .IO_WIDTH(24),
@@ -38,17 +74,25 @@ gpio #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN),
+    .BUS_DATA_OUT(BUS_DATA_OUT_1),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
     .IO(IO)
 );
 
-assign IO[15:8] = IO[7:0];
-assign IO[23:20] = IO[19:16];
-
 wire [15:0] IO_2;
+assign IO_2 = 16'ha5cd;
+
+`ifndef BASIL_SBUS
 gpio #(
+`else
+gpio_sbus #(
+`endif
     .BASEADDR(GPIO2_BASEADDR),
     .HIGHADDR(GPIO2_HIGHADDR),
     .IO_WIDTH(16),
@@ -57,16 +101,22 @@ gpio #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN),
+    .BUS_DATA_OUT(BUS_DATA_OUT_2),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
     .IO(IO_2)
 );
-assign IO_2 = 16'ha5cd;
 
+`ifndef VERILATOR_SIM
 initial begin
     $dumpfile("gpio.vcd");
     $dumpvars(0);
 end
+`endif
 
 endmodule

tests/test_SimGpio_sbus.py

@@ -19,9 +19,9 @@
     suite = unittest.TestSuite()
 
     for test_name in test_names:
-        suite.addTest(TestSimGpio(test_name, 'test_SimGpio_sbus.v', 'basil.utils.sim.BasilSbusDriver'))
+        suite.addTest(TestSimGpio(testname=test_name, tb='test_SimGpio.v', bus_drv='basil.utils.sim.BasilSbusDriver', bus_split='sbus'))
     for test_name in test_names:
-        suite.addTest(TestSimGpio(test_name, 'test_SimGpio_sbus_top.v', 'basil.utils.sim.BasilSbusDriver'))
+        suite.addTest(TestSimGpio(testname=test_name, tb='test_SimGpio.v', bus_drv='basil.utils.sim.BasilSbusDriver', bus_split='top'))
 
     result = unittest.TextTestRunner().run(suite)
     sys.exit(not result.wasSuccessful())