PRJ: Merge branch 'development'

.travis.yml

@@ -1,9 +1,10 @@
 language: python
 python:
   - 2.7
+  - 3.7
 
 sudo: required
-dist: trusty
+dist: xenial
 
 notifications:
   slack: silab-bonn:nU3pnaHN3RJ6WRFrfjec9vPM
@@ -36,9 +37,9 @@ install:
   - conda update --yes conda
   - conda update --yes --all
   - conda info -a
-  - conda create --yes -n test-environment python=$TRAVIS_PYTHON_VERSION numpy bitarray nose pyyaml coverage
+  - conda create --yes -n test-environment python=$TRAVIS_PYTHON_VERSION numpy bitarray nose pyyaml coverage six
   - source activate test-environment
-  - pip install pyvisa pyvisa-sim coveralls cocotb
+  - pip install pyvisa pyvisa-sim coveralls cocotb==1.0.dev3
   # install basil
   - python setup.py develop
 

MANIFEST.in

@@ -1,6 +1,6 @@
 include README.* VERSION LICENSE.txt requirements.txt
 recursive-include docs *
 recursive-include examples *
-recursive-include firmware *
+recursive-include basil/firmware *
 recursive-include tests *
 recursive-include basil *.yaml

README.rst

@@ -42,15 +42,15 @@ or install via PyPI into the Python's site-packages folder (for non-developers):
 
     pip install basil_daq==version
 
-where version is a version number (e.g., 2.4.13)
+where version is a version number (e.g., 3.0.0)
 
 or install from git, when no PyPI package is available (for non-developers):
 
 .. code-block:: bash
 
     pip install git+https://github.com/SiLab-Bonn/basil.git@branch
 
-where branch is a branch name or tag (e.g., master or v2.4.13).
+where branch is a branch name or tag (e.g., master or v3.0.0).
 
 Check `.travis.yml <.travis.yml>`_ for installation/testing hints.
 

VERSION

@@ -1 +1 @@
-2.4.13
+3.0.0

basil/HL/MIO_PLL.py

@@ -8,6 +8,7 @@
 import logging
 
 from basil.HL.HardwareLayer import HardwareLayer
+import six
 
 logger = logging.getLogger(__name__)
 
@@ -128,7 +129,7 @@ def _calculateParameters(self, fout):
                 break
             for self.div in range(2, 128):
                 q_d_f = self.q_total * self.div * fout
-                if isinstance(q_d_f, (long, int)) and q_d_f > (15 * self.fref):  # = f0 * p
+                if isinstance(q_d_f, six.integer_types) and q_d_f > (15 * self.fref):  # = f0 * p
                     if int(q_d_f) % int(self.fref) == 0:  # p, q, and d found
                         self.p_total = q_d_f / self.fref
                         while self.p_total <= 16:  # counter constraint

basil/HL/RegisterHardwareLayer.py

@@ -10,7 +10,9 @@
 import collections
 import array
 from collections import namedtuple
+from six import integer_types
 
+from basil.utils.utils import tobytes
 from basil.utils.BitLogic import BitLogic
 from basil.HL.HardwareLayer import HardwareLayer
 
@@ -46,9 +48,9 @@ def __init__(self, intf, conf):
         # require interface and base address
         self._intf = intf
         self._base_addr = conf['base_addr']
-        rv = namedtuple('_register_values', field_names=self._registers.iterkeys())
+        rv = namedtuple('_register_values', field_names=iter(self._registers.keys()))
         self._register_values = rv(*([None] * len(self._registers)))
-        for reg in self._registers.iterkeys():
+        for reg in self._registers.keys():
             if not reg.isupper():
                 raise ValueError("Register %s must be uppercase." % reg)
             self.add_property(reg)
@@ -65,7 +67,7 @@ def init(self):
         logger.info("Initializing %s (firmware version: %s), module %s, base_addr %s" % (self.name, version if 'VERSION' in self._registers else 'n/a', self.__class__.__module__, hex(self._base_addr)))
         if self._require_version and not eval(version + self._require_version):
             raise Exception("FPGA module %s does not satisfy version requirements (read: %s, require: %s)" % (self.__class__.__module__, version, self._require_version.strip()))
-        for reg, value in self._registers.iteritems():
+        for reg, value in self._registers.items():
             if reg in self._init:
                 self[reg] = self._init[reg]
             elif 'default' in value and not ('properties' in value['descr'] and [i for i in read_only if i in value['descr']['properties']]):
@@ -103,7 +105,7 @@ def set_value(self, value, addr, size, offset, **kwargs):
         else:
             ret = self._intf.read(self._base_addr + addr + div_offset, size=div_size)
             reg = BitLogic()
-            reg.frombytes(ret.tostring())
+            reg.frombytes(tobytes(ret))
         reg[size + mod_offset - 1:mod_offset] = value
         self._intf.write(self._base_addr + addr + div_offset, data=array.array('B', reg.tobytes()))
 
@@ -130,7 +132,7 @@ def get_value(self, addr, size, offset, **kwargs):
             div_size += 1
         ret = self._intf.read(self._base_addr + addr + div_offset, size=div_size)
         reg = BitLogic()
-        reg.frombytes(ret.tostring())
+        reg.frombytes(tobytes(ret))
         return reg[size + mod_offset - 1:mod_offset].tovalue()
 
     def set_bytes(self, data, addr, **kwargs):
@@ -168,12 +170,12 @@ def get_bytes(self, addr, size, **kwargs):
 
     def set_configuration(self, conf):
         if conf:
-            for reg, value in conf.iteritems():
+            for reg, value in conf.items():
                 self[reg] = value
 
     def get_configuration(self):
         conf = {}
-        for reg in self._registers.iterkeys():
+        for reg in self._registers.keys():
             descr = self._registers[reg]['descr']
             if not ('properties' in descr and [i for i in write_only if i in descr['properties']]) and not ('properties' in descr and [i for i in read_only if i in descr['properties']]):
                 conf[reg] = self[reg]
@@ -189,21 +191,21 @@ def add_property(self, attribute):
         def getter(self):
             try:
                 return self._get(attribute)
-            except Exception, e:
+            except Exception as e:
                 logger.error(e)
                 return None
 
         def setter(self, value):
             try:
                 return self._set(attribute, value)
-            except Exception, e:
+            except Exception as e:
                 logger.error(e)
                 return None
         # construct property attribute and add it to the class
         setattr(self.__class__, attribute, property(fget=getter, fset=setter, doc=attribute + ' register'))
 
     def set_default(self):
-        for reg, value in self._registers.iteritems():
+        for reg, value in self._registers.items():
             if 'default' in value and not ('properties' in value['descr'] and [i for i in read_only if i in self._registers[reg]['descr']['properties']]):
                 self._set(reg, value['default'])
 
@@ -247,7 +249,7 @@ def _set(self, reg, value):
             self._register_values = self._register_values._replace(**{reg: value})
         else:
             descr.setdefault('offset', 0)
-            value = value if isinstance(value, (int, long)) else int(value, base=2)
+            value = value if isinstance(value, integer_types) else int(value, base=2)
             try:
                 self.set_value(value, **descr)
             except ValueError:

basil/HL/SussProber.py

@@ -33,13 +33,13 @@ def move_position(self, dx, dy, speed=None):
 
     def get_position(self):
         ''' Read chuck position (x, y, z)'''
-        reply = self._intf.query('ReadChuckPosition Y H')
-        return [float(i) for i in reply[2:].split()]
+        reply = self._intf.query('ReadChuckPosition Y H')[2:]
+        return [float(i) for i in reply.split()]
 
     def goto_die(self, index_x, index_y):
         ''' Move chuck to wafer map chip index'''
         self._intf.write('StepNextDie %d %d' % (index_x, index_y))
-        
+
     def goto_next_die(self):
         ''' Move chuck to next die from wafer map'''
         self._intf.write('StepNextDie')
@@ -52,7 +52,7 @@ def get_die(self):
         ''' Move chuck to wafer map chip index'''
         reply = self._intf.query('ReadMapPosition')
         values = reply[2:].split(' ')
-        return (values[0], values[1])
+        return (int(values[0]), int(values[1]))
 
     def contact(self):
         ''' Move chuck to contact z position'''
@@ -61,7 +61,7 @@ def contact(self):
     def separate(self):
         ''' Move chuck to separation z position'''
         self._intf.write('MoveChuckSeparation')
-        
+
     def load(self):
         ''' Move chuck to load z position'''
         self._intf.write('MoveChuckLoad')

basil/HL/binder_mk53.py

@@ -119,7 +119,7 @@ def _parse_read_response(self, msgbytes):
             raise RuntimeWarning('Checksum of read data wrong')
         n_words = n_bytes >> 1
         words = []
-        for word in xrange(n_words):
+        for word in range(n_words):
             words.extend(struct.unpack('>H', msgbytes[3 + word * 2:5 + word * 2]))
         return words
 
@@ -168,8 +168,8 @@ def _decode_float(self, value):
     def _calc_crc16(self, msg):
         crc = 0xffff
         for byte in msg:
-            crc ^= ord(byte)
-            for _ in xrange(8):  # loop bits
+            crc ^= byte
+            for _ in range(8):  # loop bits
                 sbit = crc & 1
                 crc >>= 1
                 crc ^= sbit * 0xA001

basil/HL/bram_fifo.py

@@ -45,7 +45,7 @@ def FIFO_INT_SIZE(self):
         '''
         fifo_size = self.FIFO_SIZE
         # sometimes reading of FIFO size happens during writing to BRAM, but we want to have a multiplicity of 32 bits
-        return (fifo_size - (fifo_size % 4)) / 4
+        return int((fifo_size - (fifo_size % 4)) / 4)
 
     def get_FIFO_INT_SIZE(self):
         ''' Get FIFO size in units of integers (32 bit).

basil/HL/gpio.py

@@ -22,7 +22,7 @@ def __init__(self, intf, conf):
         if 'size' in conf.keys():
             self._size = conf['size']
 
-        io_bytes = ((self._size - 1) / 8) + 1
+        io_bytes = int(((self._size - 1) / 8) + 1)
 
         self._registers['INPUT'] = {'descr': {'addr': 1, 'size': io_bytes, 'properties': ['ro', 'byte_array']}}
         self._registers['OUTPUT'] = {'descr': {'addr': 2 + io_bytes - 1, 'size': io_bytes, 'properties': ['byte_array']}}

basil/HL/sitcp_fifo.py

@@ -22,7 +22,7 @@ class sitcp_fifo(HardwareLayer):
 
     def __getitem__(self, name):
         if name == "RESET":
-            self._intf.reset_fifo()  # returns None
+            self._intf.reset()  # returns None
         elif name == 'VERSION':
             return self._version
         elif name == 'FIFO_SIZE':
@@ -32,7 +32,7 @@ def __getitem__(self, name):
 
     def __setitem__(self, name, value):
         if name == "RESET":
-            self._intf.reset_fifo()
+            self._intf.reset()
         else:
             super(sitcp_fifo, self).__setitem__(name, value)
 
@@ -67,7 +67,7 @@ def get_data(self):
             Array of unsigned integers (32 bit).
         '''
         fifo_size = self._intf._get_tcp_data_size()
-        fifo_int_size = (fifo_size - (fifo_size % 4)) / 4
+        fifo_int_size = int((fifo_size - (fifo_size % 4)) / 4)
         data = self._intf._get_tcp_data(fifo_int_size * 4)
         return np.frombuffer(data, dtype=np.dtype('<u4'))
 

basil/HL/sram_fifo.py

@@ -62,7 +62,7 @@ def FIFO_INT_SIZE(self):
         '''
         fifo_size = self.FIFO_SIZE
         # sometimes reading of FIFO size happens during writing to SRAM, but we want to have a multiplicity of 32 bits
-        return (fifo_size - (fifo_size % 4)) / 4
+        return int((fifo_size - (fifo_size % 4)) / 4)
 
     def get_fifo_int_size(self):
         ''' *Deprecated* Get FIFO size in units of integers (32 bit).

basil/HL/tti_ql355tp.py

@@ -5,13 +5,14 @@
 # ------------------------------------------------------------
 #
 
+from __future__ import print_function
 import time
 
 from basil.HL.RegisterHardwareLayer import HardwareLayer
 
 
 class ttiQl355tp(HardwareLayer):
-    ''' HL for the TTi QL3335TP.
+    ''' HL for the TTi QL355TP.
     '''
 
     def __init__(self, intf, conf):
@@ -34,7 +35,7 @@ def ask(self, command):
     def read(self):
         ret = self._intf.read()
         if ret[-2:] != "\r\n":
-            print "ttiTp355tp.read() terminator error"
+            print("ttiTp355tp.read() terminator error")
         return ret[:-2]
 
     def set_enable(self, on, channel=1):
@@ -45,48 +46,48 @@ def set_enable(self, on, channel=1):
             cmd = "OP%d %d" % (channel, int(on))
         self.write(cmd)
 
-    def get_info(self):
+    def get_name(self):
         return self.ask("*IDN?")
 
     def get_current(self, channel):
-        """ channel: 1=OP1, 2=OP2, AUX is not suppoted"""
+        """ channel: 1=OP1, 2=OP2, AUX is not supported"""
         ret = self.ask("I%dO?" % channel)
         if ret[-1] != "A":
-            print "ttiQl355tp.get_current() format error", ret
+            print("ttiQl355tp.get_current() format error", ret)
             return None
         return float(ret[:-1])
 
     def get_voltage(self, channel):
-        """ channel: 1=OP1, 2=OP2, AUX is not suppoted"""
+        """ channel: 1=OP1, 2=OP2, AUX is not supported"""
         ret = self.ask("V%dO?" % channel)
         if ret[-1] != "V":
-            print "ttiQl355tp.get_voltage() format error", ret
+            print("ttiQl355tp.get_voltage() format error", ret)
             return None
         return float(ret[:-1])
 
     def get_set_voltage(self, channel):
-        """ channel: 1=OP1, 2=OP2, AUX is not suppoted"""
+        """ channel: 1=OP1, 2=OP2, AUX is not supported"""
         ret = self.ask("V%d?" % channel)
         if ret[:3] != "V%d " % channel:
-            print "ttiQl355tp.get_voltage() format error", ret
+            print("ttiQl355tp.get_voltage() format error", ret)
             return None
         return float(ret[3:])
 
     def get_current_limit(self, channel):
-        """ channel: 1=OP1, 2=OP2, AUX is not suppoted"""
+        """ channel: 1=OP1, 2=OP2, AUX is not supported"""
         ret = self.ask("I%d?" % channel)
         if ret[:3] != "I%d " % channel:
-            print "ttiQl355tp.get_current_limit() format error", ret
+            print("ttiQl355tp.get_current_limit() format error", ret)
             return None
         return float(ret[3:])
 
     def set_voltage(self, value, channel=1):
-        """ channel: 1=OP1, 2=OP2, AUX is not suppoted"""
+        """ channel: 1=OP1, 2=OP2, AUX is not supported"""
         cmd = "V%d %f" % (channel, value)
         self.write(cmd)
 
     def set_current_limit(self, value, channel=1):
-        """ channel: 1=OP1, 2=OP2, AUX is not suppoted"""
+        """ channel: 1=OP1, 2=OP2, AUX is not supported"""
         cmd = "I%d %f" % (channel, value)
         self.write(cmd)
 

basil/HL/tti_ql335tp.yaml → basil/HL/tti_ql355tp.yaml

@@ -1,4 +1,4 @@
-# Device description for the TTi QL335 Power Supply.
+# Device description for the TTi QL355 Power Supply.
 identifier : QL355TP
 on : OPALL 1
 off : OPALL 0

basil/HL/weiss_sb22.py

@@ -131,7 +131,7 @@ def check_for_errors(self, answer):
 
     def _calc_crc(self, msg):
         ASCII = "0123456789ABCDEF"
-        mod_256 = (-(sum(ord(i) for i in msg) % 256) & 0xFF)
+        mod_256 = (-(sum(i for i in msg) % 256) & 0xFF)
         lword = (mod_256 & 0xF0) >> 4
         hword = mod_256 & 0x0F
         return ASCII[lword] + ASCII[hword]