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SiN design rev0
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Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
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Please run verification "v" in KLayout SiEPIC-Tools. There are lots of critical errors, so no, your design cannot be accepted as is.
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Errors fixed on my side. |
New SiN Design with different coupling
third SiN design
updated versions with corrected DC layout
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Hi, I added three SiN MDM layouts. Please let me know if there are any issues that prevent merging. |
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SiN design rev0. DR fails due to modification of the rings from python file. Is it possible to override this DR error?