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Symmetric Multiprocessing

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Sukant Pal edited this page Dec 3, 2017 · 1 revision

SMP

Introduction

SMP, or symmetric multiprocessing, is a technique used in computer hardware and system software to execute multiple code paths in a parallel fashion. Any system with multiple CPUs is a SMP-compatible system. Generally, large SMP systems distribute physical memory into nodes (NUMA) where each group of CPUs can access a memory node. To access a memory node attached to the other NUMA group (of processors), the CPUs co-operate and signal each other instead of the external CPU directly accessing the NUMA node. This kernel implements UMA SMP (right now), where no NUMA-nodes are taken into consideration and all CPUs can access the memory.

BSP

BSP, or 'Bootstrap Processor', is a CPU that is selected at power-up by the firmware which loads the BIOS/EFI and drives the boot process. So that means during boot-time, only one CPU (BSP only) is on and all other processors are dormant.

AP

AP, or 'Application Processor', is any CPU other than the BSP. It is woken up by the kernel during boot-time and is dormant until the kernel loads. Application processors startup in real-mode in lower-memory.

How does the kernel wake-up other CPUs?

SMP support is something which is architectural and which is heavily dependent on the HAL. The following files are related to SMP support in the microkernel -

 Arch/IA32/HAL/APBoot.asm
 Arch/IA32/HAL/Processor.cpp

IA32

Kernel tries to wake-up all application processors that were registered into the MADT (Multiple APIC Descriptor Table). The kernel follows these steps to wake-up all APs -

  1. Using CPUID, check support for x2APIC mode; if not supported, map the xAPIC registers into a non-cacheable kernel address. Otherwise, setup x2APICMode to TRUE.

  2. Construct the BSP's per-CPU struct using the its own PROCESSOR_ID (given by xAPIC/x2APIC registers).

  3. Disable the PIC (Programmable Interrupt Controller), and setup the IDT (all CPUs share one IDT) and follow the standard processor-setup routine for the BSP (load GDT, IDT, and TSS)

  4. Setup the early APIC-timer which ticks at larger intervals. This allows checking whether an AP has woken after sending a INIT signal.

  5. Initialize CMOS registers related to booting the APs.

  6. When the kernel is ready to wake-up APs, the MADT is parsed and registered processors are sent a INIT-SIPI signal and a trampoline (containing startup code) is copied at a 16-bit physical address (0x1000 aligned).

  7. If the AP wakes up, it will execute trampoline code, otherwise the BSP continues.

How do the APs setup themselves OR What is in the trampoline?

The trampoline contains the code to setup a minimal GDT (in the trampoline itself), setup pagination (first using the identity page), and then using its APIC_ID it setups its stack (see Processor::Hardware::ProcessorStack). From there, a AP registers itself in the processor topology and waits for the BSP to unlock the AP-permit for enabling scheduling. From there, all CPUs run a init-thread & idle-thread.

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