This project describes Verilog code for a 32-bit pipelined MIPS processor.
It is a combination of gate-level, dataflow and behavioural modelling.
Features:
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Instruction Memory for 32-bit MIPS instructions.
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32 32-bit Data Memory locations.
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Instruction Memory consisting of arithmetic, logical, branch, jump, and memory-access instructions. Immediate arguments and argument registers are hard-coded.
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5-stage pipelining; stages are: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), Writeback (WB).
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Data Forwarding Unit to partially resolve hazards in R-type instructions.
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Hazard Detection Unit to insert stalls (nop cycles) wherever required.