GitHub - SambhavSaxena-1107/Logic-Gates-Verification-using-Test-Bench

Name		Name	Last commit message	Last commit date
Latest commit History 16 Commits
AND Verification.png		AND Verification.png
NAND Verification.png		NAND Verification.png
NOR Verification.png		NOR Verification.png
NOT Verification.png		NOT Verification.png
OR Verification.png		OR Verification.png
Test_Bench.pdf		Test_Bench.pdf
and_design.v		and_design.v
and_test.v		and_test.v
nand_design.v		nand_design.v
nand_test.v		nand_test.v
nor_design.v		nor_design.v
nor_test.v		nor_test.v
not_design.v		not_design.v
not_test.v		not_test.v
or_design.v		or_design.v
or_test.v		or_test.v