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201807 #59

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Mar 14, 2019
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5e48e6c
[barefoot]: Update bfn deb pkg urls for 201807 (#1963)
mkbalani Aug 22, 2018
f07181e
[201807][platform] Accton: As5712-54x. Fix sfputil and accton_util (…
roylee123 Aug 30, 2018
90257f5
[devices]: Update 201807 release with transceiver detection for arist…
zzhiyuan Sep 5, 2018
be56470
[Mellanox] Update hw-management service config (#2019)
andriymoroz-mlnx Sep 6, 2018
dd94d9d
[mellanox]: Fix qos.json.j2: apply qos config for active ports (#1932)
stepanblyschak Aug 16, 2018
6293178
[mlnx-sfp-plugin] enhancement to support transceiver sensor monitorin…
keboliu Aug 2, 2018
e237df8
[docker-platform-monitor] make file and supervisord conf change for n…
keboliu Aug 3, 2018
97b5f3d
update sonic-platform-common submodule for xcvrd support (#1901)
keboliu Aug 6, 2018
8fc6874
[mlnx-platform] enhancement for xcvrd implementation on mlnx platform…
keboliu Aug 17, 2018
bc4a39f
[swsssdk]: update DBInterface submodule (#1942)
keboliu Aug 17, 2018
6cf2d10
[snmpagent]: update snmpagent submodule
lguohan Sep 6, 2018
0aeba8a
[devices]: Update arista driver submodule (#2057)
Staphylo Sep 19, 2018
2ffbb0e
[barefoot]: Fix bfn sde dep (#2086)
mkbalani Sep 27, 2018
786a908
[submodules]: update sonic-linux-kernel
lguohan Oct 3, 2018
352532a
[submodule]: update sonic-linux-kernel
lguohan Oct 3, 2018
fd7c190
[submodules] update dbsyncd and snmpagent pointers for LLDP MIB support
Sep 26, 2018
c2b1cae
[arista] Update Arista drivers submodule (#2107)
Staphylo Oct 4, 2018
182c351
[devices]: Update arista submodules for SFP txdisable toggle (#2123)
zzhiyuan Oct 5, 2018
12fe300
[devices]: Align flash partition at 1M (#2104)
Staphylo Oct 2, 2018
56b8a2c
[centec]: update centec platform driver and device data (#2060)
yangbashuang Oct 16, 2018
83c2115
[devices]: Update arista driver submodule (#2251)
Staphylo Nov 16, 2018
b818397
Dell submodule update for depmod fixes (#2292)
Nov 22, 2018
2ffa1e9
[Mellanox] Update hw-management service config (#2325)
kevinwangsk Dec 1, 2018
9a64452
Store thrift source packages in blob (#2255)
qiluo-msft Nov 14, 2018
8b6d69a
Fix bug: wget rename saved file (#2259)
qiluo-msft Nov 15, 2018
4af5328
[thrift]: change wget download from -nc to -N (#2268)
lguohan Nov 18, 2018
fea4bdf
Fix redis-py version to 2.10.6 (#2342)
kevinwangsk Dec 4, 2018
c164caf
update sdk and sai for 201807 (#2330)
simonJi2018 Dec 4, 2018
a1e6c2c
Add Pegatron project to branch 201807 (#2299)
Peter5Lin Dec 4, 2018
315b976
Merge pull request #14 from Azure/201807
bbinxie Dec 25, 2018
6bf252f
[devices]: Fix arista-convertfs for aligning flash via sfdisk in Jess…
shawnli-van Dec 28, 2018
d9c7e94
Merge pull request #51 from Azure/201807
Alex-Dai Feb 22, 2019
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66 changes: 53 additions & 13 deletions device/accton/x86_64-accton_as5712_54x-r0/plugins/sfputil.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,9 +2,9 @@
#
# Platform-specific SFP transceiver interface for SONiC
#

try:
import time
import os
from sonic_sfp.sfputilbase import SfpUtilBase
except ImportError as e:
raise ImportError("%s - required module not found" % str(e))
Expand All @@ -21,8 +21,14 @@ class SfpUtil(SfpUtilBase):

BASE_VAL_PATH = "/sys/class/i2c-adapter/i2c-{0}/{1}-0050/"
BASE_OOM_PATH = "/sys/bus/i2c/devices/{0}-0050/"
BASE_CPLD2_PATH = "/sys/bus/i2c/devices/0-0061/"
BASE_CPLD3_PATH = "/sys/bus/i2c/devices/0-0062/"
BASE_CPLD2_PATH = "/sys/bus/i2c/devices/{0}-0061/"
BASE_CPLD3_PATH = "/sys/bus/i2c/devices/{0}-0062/"
I2C_BUS_ORDER = -1

#The sidebands of QSFP is different.
#present is in-order.
#But lp_mode and reset are not.
qsfp_sb_map = [1, 3, 5, 2, 4, 6]

_port_to_is_present = {}
_port_to_lp_mode = {}
Expand Down Expand Up @@ -137,18 +143,30 @@ def __init__(self):

SfpUtilBase.__init__(self)

#Two i2c buses might get flipped order, check them both.
def update_i2c_order(self):
if self.I2C_BUS_ORDER < 0:
eeprom_path = "/sys/bus/i2c/devices/1-0057/eeprom"
if os.path.exists(eeprom_path):
self.I2C_BUS_ORDER = 0
eeprom_path = "/sys/bus/i2c/devices/0-0057/eeprom"
if os.path.exists(eeprom_path):
self.I2C_BUS_ORDER = 1
return self.I2C_BUS_ORDER

def get_presence(self, port_num):
# Check for invalid port_num
if port_num < self.port_start or port_num > self.port_end:
return False

order = self.update_i2c_order()
if port_num < 24:
present_path = self.BASE_CPLD2_PATH + "module_present_" + str(self._port_to_i2c_mapping[port_num][0])
present_path = self.BASE_CPLD2_PATH.format(order)
else:
present_path = self.BASE_CPLD3_PATH + "module_present_" + str(self._port_to_i2c_mapping[port_num][0])
present_path = self.BASE_CPLD3_PATH.format(order)

present_path = present_path + "module_present_" + str(self._port_to_i2c_mapping[port_num][0])
self.__port_to_is_present = present_path


try:
val_file = open(self.__port_to_is_present)
Expand All @@ -165,11 +183,21 @@ def get_presence(self, port_num):

return False

def qsfp_sb_remap(self, port_num):
qsfp_start = self.qsfp_port_start
qsfp_index = self._port_to_i2c_mapping[port_num][0] - qsfp_start
qsfp_index = self.qsfp_sb_map[qsfp_index-1]
return qsfp_start+qsfp_index

def get_low_power_mode(self, port_num):
if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
return False

lp_mode_path = self.BASE_CPLD3_PATH + "module_lp_mode_" + str(self._port_to_i2c_mapping[port_num][0])
order = self.update_i2c_order()
lp_mode_path = self.BASE_CPLD3_PATH.format(order)
lp_mode_path = lp_mode_path + "module_lp_mode_"
q = self.qsfp_sb_remap(port_num)
lp_mode_path = lp_mode_path + str(q)

try:
val_file = open(lp_mode_path)
Expand All @@ -190,7 +218,11 @@ def set_low_power_mode(self, port_num, lpmode):
if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
return False

lp_mode_path = self.BASE_CPLD3_PATH + "module_lp_mode_" + str(self._port_to_i2c_mapping[port_num][0])
order = self.update_i2c_order()
lp_mode_path = self.BASE_CPLD3_PATH.format(order)
lp_mode_path = lp_mode_path + "module_lp_mode_"
q = self.qsfp_sb_remap(port_num)
lp_mode_path = lp_mode_path + str(q)

try:
reg_file = open(lp_mode_path, 'r+')
Expand All @@ -212,17 +244,25 @@ def reset(self, port_num):
if port_num < self.qsfp_port_start or port_num > self.qsfp_port_end:
return False

mod_rst_path = lp_mode_path = self.BASE_CPLD3_PATH + "module_reset_" + str(self._port_to_i2c_mapping[port_num][0])
order = self.update_i2c_order()
lp_mode_path = self.BASE_CPLD3_PATH.format(order)
mod_rst_path = lp_mode_path + "module_reset_"
q = self.qsfp_sb_remap(port_num)
mod_rst_path = mod_rst_path + str(q)

try:
reg_file = open(mod_rst_path, 'r+')
except IOError as e:
print "Error: unable to open file: %s" % str(e)
return False

reg_value = '1'

reg_file.write(reg_value)
#toggle reset
reg_file.seek(0)
reg_file.write('0')
time.sleep(1)
reg_file.seek(0)
reg_file.write('1')
reg_file.close()
return True

return True
return True
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
{%- set default_topo = 't0' %}
{%- include 'buffers_config.j2' %}
Original file line number Diff line number Diff line change
@@ -0,0 +1,72 @@
{% set default_cable = '5m' %}
{% set ingress_lossless_pool_size = '20971328' %}
{% set ingress_lossy_pool_size = '20971328' %}
{% set egress_lossless_pool_size = '20971328' %}
{% set egress_lossy_pool_size = '20971328' %}

{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0, 48) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %}
{%- endfor %}
{%- for port_idx in range(48, 54) %}
{%- if PORT_ALL.append("Ethernet%d" % (48 + (port_idx-48) * 4)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}

{%- macro generate_buffer_pool_and_profiles() %}
"BUFFER_POOL": {
"ingress_lossless_pool": {
"size": "{{ ingress_lossless_pool_size }}",
"type": "ingress",
"mode": "dynamic"
},
"ingress_lossy_pool": {
"size": "{{ ingress_lossy_pool_size }}",
"type": "ingress",
"mode": "dynamic"
},
"egress_lossless_pool": {
"size": "{{ egress_lossless_pool_size }}",
"type": "egress",
"mode": "dynamic"
},
"egress_lossy_pool": {
"size": "{{ egress_lossy_pool_size }}",
"type": "egress",
"mode": "dynamic"
}
},
"BUFFER_PROFILE": {
"ingress_lossless_profile": {
"pool":"[BUFFER_POOL|ingress_lossless_pool]",
"xon":"78400",
"xoff":"132160",
"size":"3584",
"static_th":"82880"
},
"ingress_lossy_profile": {
"pool":"[BUFFER_POOL|ingress_lossy_pool]",
"size":"3584",
"dynamic_th":"-1"
},
"egress_lossy_profile": {
"pool":"[BUFFER_POOL|egress_lossy_pool]",
"size":"3584",
"dynamic_th":"-4"
}
},
{%- endmacro %}

{# the typo of generate_pg_profils dued to buffers_config.j2 #}
{# Default, we do not bind any buffer profiles. #}
{%- macro generate_pg_profils(port_names) %}
"BUFFER_PG": {
}
{%- endmacro %}

{# Default, we do not bind any buffer profiles. #}
{%- macro generate_queue_buffers(port_names) %}
"BUFFER_QUEUE": {
}
{%- endmacro %}
Original file line number Diff line number Diff line change
@@ -0,0 +1,72 @@
{% set default_cable = '5m' %}
{% set ingress_lossless_pool_size = '20971328' %}
{% set ingress_lossy_pool_size = '20971328' %}
{% set egress_lossless_pool_size = '20971328' %}
{% set egress_lossy_pool_size = '20971328' %}

{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0, 48) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %}
{%- endfor %}
{%- for port_idx in range(48, 54) %}
{%- if PORT_ALL.append("Ethernet%d" % (48 + (port_idx-48) * 4)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}

{%- macro generate_buffer_pool_and_profiles() %}
"BUFFER_POOL": {
"ingress_lossless_pool": {
"size": "{{ ingress_lossless_pool_size }}",
"type": "ingress",
"mode": "dynamic"
},
"ingress_lossy_pool": {
"size": "{{ ingress_lossy_pool_size }}",
"type": "ingress",
"mode": "dynamic"
},
"egress_lossless_pool": {
"size": "{{ egress_lossless_pool_size }}",
"type": "egress",
"mode": "dynamic"
},
"egress_lossy_pool": {
"size": "{{ egress_lossy_pool_size }}",
"type": "egress",
"mode": "dynamic"
}
},
"BUFFER_PROFILE": {
"ingress_lossless_profile": {
"pool":"[BUFFER_POOL|ingress_lossless_pool]",
"xon":"78400",
"xoff":"132160",
"size":"3584",
"static_th":"82880"
},
"ingress_lossy_profile": {
"pool":"[BUFFER_POOL|ingress_lossy_pool]",
"size":"3584",
"dynamic_th":"-1"
},
"egress_lossy_profile": {
"pool":"[BUFFER_POOL|egress_lossy_pool]",
"size":"3584",
"dynamic_th":"-4"
}
},
{%- endmacro %}

{# the typo of generate_pg_profils dued to buffers_config.j2 #}
{# Default, we do not bind any buffer profiles. #}
{%- macro generate_pg_profils(port_names) %}
"BUFFER_PG": {
}
{%- endmacro %}

{# Default, we do not bind any buffer profiles. #}
{%- macro generate_queue_buffers(port_names) %}
"BUFFER_QUEUE": {
}
{%- endmacro %}
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
# PG lossless profiles.
# speed cable size xon xoff threshold
10000 5m 3584 32256 59136 36736
25000 5m 3584 41216 68096 45696
40000 5m 3584 47488 74368 51968
50000 5m 3584 52864 79744 57344
100000 5m 3584 78400 132160 82880
10000 40m 3584 32256 59136 36736
25000 40m 3584 41216 68096 45696
40000 40m 3584 47488 74368 51968
50000 40m 3584 52864 79744 57344
100000 40m 3584 78400 132160 82880
10000 300m 3584 32256 65856 36736
25000 300m 3584 41216 84672 45696
40000 300m 3584 47488 101024 51968
50000 300m 3584 52864 113120 57344
100000 300m 3584 78400 198688 82880
Original file line number Diff line number Diff line change
Expand Up @@ -47,12 +47,9 @@ Ethernet44 76 Ethernet45/1 44
Ethernet45 77 Ethernet46/1 45
Ethernet46 78 Ethernet47/1 46
Ethernet47 79 Ethernet48/1 47
Ethernet48 80 Ethernet49/1 48
Ethernet49 81 Ethernet50/1 49
Ethernet50 82 Ethernet51/1 50
Ethernet51 83 Ethernet52/1 51
Ethernet52 84,85,86,87 Ethernet53/1 52
Ethernet53 104,105,106,107 Ethernet54/1 53
Ethernet54 108,109,110,111 Ethernet55/1 54
Ethernet55 112,113,114,115 Ethernet56/1 55
Ethernet56 116,117,118,119 Ethernet57/1 56
Ethernet48 84,85,86,87 Ethernet49/1 48
Ethernet49 80,81,82,83 Ethernet50/1 49
Ethernet50 104,105,106,107 Ethernet51/1 50
Ethernet51 108,109,110,111 Ethernet52/1 51
Ethernet52 112,113,114,115 Ethernet53/1 52
Ethernet53 116,117,118,119 Ethernet54/1 53
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