UsartSpi Support

avr-hal-generic/src/lib.rs

@@ -20,6 +20,7 @@ pub mod port;
 pub mod simple_pwm;
 pub mod spi;
 pub mod usart;
+pub mod usart_spi;
 pub mod wdt;
 
 /// Prelude containing all HAL traits

avr-hal-generic/src/spi.rs

@@ -1,5 +1,5 @@
 //! SPI Implementation
-use crate::port;
+use crate::{port, usart::UsartOps};
 use core::marker::PhantomData;
 use embedded_hal::spi::{self, SpiBus};
 
@@ -200,6 +200,42 @@ pub struct Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> {
     _h: PhantomData<H>,
 }
 
+impl<H, USART, SCLKPIN, MOSIPIN, MISOPIN, UsartSPIDummyPin>
+    Spi<H, USART, SCLKPIN, MOSIPIN, MISOPIN, UsartSPIDummyPin>
+where
+    USART: SpiOps<H, SCLKPIN, MOSIPIN, MISOPIN, UsartSPIDummyPin>
+        + UsartOps<H, port::Pin<port::mode::Input, MISOPIN>, port::Pin<port::mode::Output, MOSIPIN>>,
+    SCLKPIN: port::PinOps,
+    MOSIPIN: port::PinOps,
+    MISOPIN: port::PinOps,
+{
+    /// Instantiate a USART based SPI with the registers, SCLK/MOSI/MISO pins, and settings,
+    /// with the internal pull-up enabled on the MISO pin.
+    ///
+    /// The pins are not actually used directly, but they are moved into the struct in
+    /// order to enforce that they are in the correct mode, and cannot be used by anyone
+    /// else while SPI is active.
+    pub fn new_from_usart(
+        p: USART,
+        sclk: port::Pin<port::mode::Output, SCLKPIN>,
+        mosi: port::Pin<port::mode::Output, MOSIPIN>,
+        miso: port::Pin<port::mode::Input<port::mode::PullUp>, MISOPIN>,
+        settings: Settings,
+    ) -> Self {
+        let mut spi = Self {
+            p,
+            sclk,
+            mosi,
+            miso: miso.forget_imode(),
+            write_in_progress: false,
+            _cs: PhantomData,
+            _h: PhantomData,
+        };
+        spi.p.raw_setup(&settings);
+        spi
+    }
+}
+
 impl<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN> Spi<H, SPI, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>
 where
     SPI: SpiOps<H, SCLKPIN, MOSIPIN, MISOPIN, CSPIN>,

avr-hal-generic/src/usart_spi.rs

@@ -0,0 +1,132 @@
+//! MSPIM Implimentation
+use crate::{port::PinOps, spi};
+
+// This module just implements a macro for SpiOps, since underlyingly, the Spi type can still be used since it just needs SpiOps
+
+/// Dummy Pin for MPSPIM
+pub struct UsartSPIDummyPin;
+
+impl PinOps for UsartSPIDummyPin {
+    type Dynamic = Self;
+
+    fn into_dynamic(self) -> Self::Dynamic {
+        self
+    }
+
+    unsafe fn out_set(&mut self) {}
+
+    unsafe fn out_clear(&mut self) {}
+
+    unsafe fn out_toggle(&mut self) {}
+
+    unsafe fn out_get(&self) -> bool {
+        false
+    }
+
+    unsafe fn in_get(&self) -> bool {
+        true
+    }
+
+    unsafe fn make_output(&mut self) {}
+
+    unsafe fn make_input(&mut self, _pull_up: bool) {}
+}
+
+pub type UsartSpi<H, USART, SCLKPIN, MOSIPIN, MISOPIN> =
+    spi::Spi<H, USART, SCLKPIN, MOSIPIN, MISOPIN, UsartSPIDummyPin>;
+
+// Implement SpiOps trait for USART
+#[macro_export]
+macro_rules! add_usart_spi {
+    (
+        hal: $HAL:ty,
+        peripheral: $USART_SPI:ty,
+        register_suffix: $n:expr,
+        sclk: $sclkpin:ty,
+        mosi: $mosipin:ty,
+        miso: $misopin:ty,
+    ) => {
+        $crate::paste::paste! {
+            // This is quite a messy way to get the doc string working properly... but it works!
+            #[doc = concat!("**Clock:** `", stringify!($sclkpin), "`<br>**MOSI:** `", stringify!($mosipin), "`<br> **MISO:** `", stringify!($misopin), "`")]
+            pub type [<Usart $n Spi>] = avr_hal_generic::usart_spi::UsartSpi<$HAL, $USART_SPI, $sclkpin, $mosipin, $misopin>;
+
+            impl $crate::spi::SpiOps<$HAL, $sclkpin, $mosipin, $misopin, $crate::usart_spi::UsartSPIDummyPin> for $USART_SPI {
+                fn raw_setup(&mut self, settings: &$crate::spi::Settings) {
+                    use $crate::hal::spi;
+
+                    // UBRRn must be zero at the time the transmitter is enabled.
+                    self.[<ubrr $n>].write(|w| unsafe {w.bits(0)});
+
+                    // We have to translate the character size register into the 2 bits which are the MSB/LSB and the phase
+                    // 5 Bit Char = MSB and 1st
+                    // 6 Bit Char = MSB and 2nd
+                    // 7 Bit Char = LSB and 1st
+                    // 8 Bit Char = LSB and 2nd
+                    self.[<ucsr $n c>].write(|w| {
+                        w.[<umsel $n>]().spi_master();
+
+                        match settings.data_order {
+                            $crate::spi::DataOrder::MostSignificantFirst => match settings.mode.phase {
+                                spi::Phase::CaptureOnFirstTransition => w.[<ucsz $n>]().chr5(),
+                                spi::Phase::CaptureOnSecondTransition => w.[<ucsz $n>]().chr6(),
+                            },
+                            $crate::spi::DataOrder::LeastSignificantFirst => match settings.mode.phase {
+                                spi::Phase::CaptureOnFirstTransition => w.[<ucsz $n>]().chr7(),
+                                spi::Phase::CaptureOnSecondTransition => w.[<ucsz $n>]().chr8(),
+                            },
+                        };
+
+                        match settings.mode.polarity {
+                            spi::Polarity::IdleLow => w.[<ucpol $n>]().clear_bit(),
+                            spi::Polarity::IdleHigh => w.[<ucpol $n>]().set_bit(),
+                        }
+                    });
+
+                    // Enable receiver and transmitter.
+                    self.[<ucsr $n b>].write(|w| w
+                        .[<txen $n>]().set_bit()
+                        .[<rxen $n>]().set_bit()
+                    );
+
+                    // Set the clock divider for SPI clock.
+                    // This must be done after the transmitter is enabled.
+                    self.[<ubrr $n>].write(|w| unsafe {
+                        match settings.clock {
+                            $crate::spi::SerialClockRate::OscfOver2 => w.bits(0),
+                            $crate::spi::SerialClockRate::OscfOver4 => w.bits(1),
+                            $crate::spi::SerialClockRate::OscfOver8 => w.bits(3),
+                            $crate::spi::SerialClockRate::OscfOver16 => w.bits(7),
+                            $crate::spi::SerialClockRate::OscfOver32 => w.bits(15),
+                            $crate::spi::SerialClockRate::OscfOver64 => w.bits(31),
+                            $crate::spi::SerialClockRate::OscfOver128 => w.bits(63),
+                        }
+                    });
+                }
+
+                fn raw_release(&mut self) {
+                    self.[<ucsr $n c>].write(|w| w.[<umsel $n>]().usart_async());
+                    self.[<ucsr $n b>].reset();
+                }
+
+                fn raw_check_iflag(&self) -> bool {
+                    self.[<ucsr $n a>].read().[<rxc $n>]().bit_is_set()
+                }
+
+                fn raw_read(&self) -> u8 {
+                    self.[<udr $n>].read().bits()
+                }
+
+                fn raw_write(&mut self, byte: u8) {
+                    self.[<udr $n>].write(|w| unsafe { w.bits(byte) });
+                }
+
+                fn raw_transaction(&mut self, byte: u8) -> u8 {
+                    self.raw_write(byte);
+                    while !self.raw_check_iflag() {}
+                    self.raw_read()
+                }
+            }
+        }
+    };
+}

examples/atmega2560/src/bin/atmega2560-usart_spi-feedback.rs

@@ -0,0 +1,75 @@
+//! This example demonstrates how to set up a SPI interface and communicate
+//! over it.  The physical hardware configuration consists of connecting a
+//! jumper directly from pin `PB2` to pin `PB3`.
+//!
+//! Run the program using `cargo run`.
+//! You should see it output the line `data: 42` repeatedly.
+//! If the output you see is `data: 255`, you may need to check your jumper.
+
+#![no_std]
+#![no_main]
+
+use atmega_hal::delay::Delay;
+use atmega_hal::usart::{Baudrate, Usart};
+use atmega_hal::usart_spi;
+use embedded_hal::delay::DelayNs;
+use embedded_hal::spi::SpiBus;
+use panic_halt as _;
+
+// Define core clock. This can be used in the rest of the project.
+type CoreClock = atmega_hal::clock::MHz16;
+
+#[avr_device::entry]
+fn main() -> ! {
+    let dp = atmega_hal::Peripherals::take().unwrap();
+    let pins = atmega_hal::pins!(dp);
+
+    let mut delay = Delay::<crate::CoreClock>::new();
+
+    // set up serial interface for text output
+    let mut serial = Usart::new(
+        dp.USART0,
+        pins.pe0,
+        pins.pe1.into_output(),
+        Baudrate::<crate::CoreClock>::new(57600),
+    );
+
+    // Create SPI interface.
+    let mut spi = usart_spi::Usart1Spi::new_from_usart(
+        dp.USART1,
+        pins.pd5.into_output(),
+        pins.pd3.into_output(),
+        pins.pd2.into_pull_up_input(),
+        atmega_hal::spi::Settings::default(),
+    );
+
+    // Other SPI examples for other USART's
+
+    // let mut spi = usart_spi::Usart2Spi::new_from_usart(
+    //     dp.USART2,
+    //     pins.ph2.into_output(),
+    //     pins.ph1.into_output(),
+    //     pins.ph0.into_pull_up_input(),
+    //     atmega_hal::spi::Settings::default(),
+    // );
+
+    // let mut spi = usart_spi::Usart3Spi::new_from_usart(
+    //     dp.USART3,
+    //     pins.pj2.into_output(),
+    //     pins.pj1.into_output(),
+    //     pins.pj0.into_pull_up_input(),
+    //     atmega_hal::spi::Settings::default(),
+    // );
+
+    loop {
+        // Send a byte
+        let data_out: [u8; 1] = [42];
+        let mut data_in: [u8; 1] = [0];
+        // Send a byte
+        // Because MISO is connected to MOSI, the read data should be the same
+        spi.transfer(&mut data_in, &data_out).unwrap();
+
+        ufmt::uwriteln!(&mut serial, "data: {}\r", data_in[0]).unwrap();
+        delay.delay_ms(1000);
+    }
+}

mcu/atmega-hal/src/lib.rs

@@ -145,6 +145,9 @@ pub mod eeprom;
 #[cfg(feature = "device-selected")]
 pub use eeprom::Eeprom;
 
+#[cfg(feature = "device-selected")]
+pub mod usart_spi;
+
 pub struct Atmega;
 
 #[cfg(any(feature = "atmega48p", feature = "atmega168", feature = "atmega328p"))]

mcu/atmega-hal/src/usart.rs

@@ -45,7 +45,8 @@ pub type UsartReader<USART, RX, TX, CLOCK> =
     feature = "atmega328p",
     feature = "atmega328pb",
     feature = "atmega1284p",
-    feature = "atmega164pa"
+    feature = "atmega164pa",
+    feature = "atmega48p"
 ))]
 pub type Usart0<CLOCK> = Usart<
     crate::pac::USART0,
@@ -58,7 +59,8 @@ pub type Usart0<CLOCK> = Usart<
     feature = "atmega328p",
     feature = "atmega328pb",
     feature = "atmega1284p",
-    feature = "atmega164pa"
+    feature = "atmega164pa",
+    feature = "atmega48p"
 ))]
 avr_hal_generic::impl_usart_traditional! {
     hal: crate::Atmega,