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cpu/sam0_common/periph/sdhc: busy waiting and clock fixes #19815
cpu/sam0_common/periph/sdhc: busy waiting and clock fixes #19815
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The only peripheral that currently uses the FDPLL1 is SDHC. However, the SDHC IP can only be clocked at up to 150 MHz. Therefore, 100 MHz is currently used as the frequency of the FDPLL1. If another peripheral device requires 200 MHz in the future, this must be realized via different clock generators.
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Looks good.
bors merge |
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Contribution description
This PR collects fixes to the sam0 SDHC driver (that soon will be replaced by
periph_sdmmc
):Testing procedure
Issues/PRs references