cpu/samd5x: add support for FDPLL1 running at 200MHz

Signed-off-by: Dylan Laduranty <dylan.laduranty@mesotic.com>

cpu/samd5x/cpu.c

@@ -252,6 +252,9 @@ void sam0_gclk_enable(uint8_t id)
             gclk_connect(SAM0_GCLK_PERIPH, GCLK_SOURCE_ACTIVE_XOSC, 0);
         }
 
+        break;
+    case SAM0_GCLK_200MHZ:
+        gclk_connect(SAM0_GCLK_200MHZ, GCLK_SOURCE_DPLL1, 0);
         break;
     }
 }
@@ -274,6 +277,8 @@ uint32_t sam0_gclk_freq(uint8_t id)
             assert(0);
             return 0;
         }
+    case SAM0_GCLK_200MHZ:
+        return MHZ(200);
     default:
         return 0;
     }
@@ -350,6 +355,7 @@ void cpu_init(void)
     xosc_init(0);
     xosc_init(1);
     fdpll_init(0, CLOCK_CORECLOCK * DPLL_DIV);
+    fdpll_init(1, MHZ(200));
 
     /* select the source of the main clock */
     if (USE_DPLL) {
@@ -387,4 +393,5 @@ void cpu_init(void)
     /* set ONDEMAND bit after all clocks have been configured */
     /* This is to avoid setting the source for the main clock to ONDEMAND before using it. */
     OSCCTRL->Dpll[0].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND;
+    OSCCTRL->Dpll[1].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND;
 }

cpu/samd5x/include/periph_cpu.h

@@ -65,6 +65,7 @@ enum {
     SAM0_GCLK_32KHZ,                    /**< 32 kHz clock             */
     SAM0_GCLK_TIMER,                    /**< 4-8 MHz clock for xTimer */
     SAM0_GCLK_PERIPH,                   /**< 12-48 MHz (DFLL) clock   */
+    SAM0_GCLK_200MHZ,                   /**< 200MHz FDPLL clock       */
 };
 /** @} */