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Merge pull request #7 from RGD2/revert-6-master
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Revert "tracking upstream"
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@RGD2
RGD2 committed May 18, 2016
2 parents b9eb59e + 71e0401 commit c349e26
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Showing 7 changed files with 70 additions and 67 deletions.
1 change: 0 additions & 1 deletion anstests/core.fr
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Expand Up @@ -553,7 +553,6 @@ T{ 1STA 2NDA U< -> <TRUE> }T \ HERE MUST GROW WITH ALLOT
T{ 1STA 1+ -> 2NDA }T \ ... BY ONE ADDRESS UNIT
( MISSING TEST: NEGATIVE ALLOT )

align
HERE 1 ,
HERE 2 ,
CONSTANT 2ND
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2 changes: 1 addition & 1 deletion esp8266/go
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Expand Up @@ -4,5 +4,5 @@ make clean
make -f Makefile
ls -l *.bin
xtensa-lx106-elf-objdump -d swapforth > 0
python esptool2.py --port /dev/white --baud 921600 write_flash 0 swapforth-0x00000.bin 0x08000 swapforth-0x08000.bin
python esptool2.py --port /dev/white --baud 1000000 write_flash 0 swapforth-0x00000.bin 0x08000 swapforth-0x08000.bin
# python esptool2.py --port /dev/white --baud 1000000 run
6 changes: 2 additions & 4 deletions esp8266/swapforth.c
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Expand Up @@ -131,8 +131,6 @@ uart0_rx_intr_handler(void *para)
}
}

#define BAUDRATE 921600

void
uart_config(uint8 uart_no)
{
Expand All @@ -145,7 +143,7 @@ uart_config(uint8 uart_no)
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
}

uart_div_modify(uart_no, UART_CLK_FREQ / BAUDRATE);
uart_div_modify(uart_no, UART_CLK_FREQ / 1000000);


//clear rx and tx fifo,not ready
Expand Down Expand Up @@ -183,7 +181,7 @@ void ICACHE_FLASH_ATTR
user_init()
{
system_set_os_print(0);
uart_div_modify(0, UART_CLK_FREQ / BAUDRATE);
uart_div_modify(0, UART_CLK_FREQ / 1000000);

// wifi_config();

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94 changes: 48 additions & 46 deletions j1a/nuc.fs
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Expand Up @@ -130,27 +130,24 @@ header .x
header execute
: execute
>r
: noop
;

header @
: @
h# 2000 or execute
;

: var: r> ; \ variable defining word

header false : false d# 0 ;
header true : true d# -1 ;
header rot : rot >r swap r> swap ;
header -rot : -rot swap >r swap var: ;
header -rot : -rot swap >r swap r> ;
header tuck : tuck swap over ;
header 2drop : 2drop drop drop ;
header ?dup : ?dup dup if dup then ;

header 2dup : 2dup over over ;
header +! : +! tuck @ + swap _! ;
header 2swap : 2swap rot >r rot var: ;
header 2swap : 2swap rot >r rot r> ;
header 2over : 2over >r >r 2dup r> r> 2swap ;

header min : min 2dup<
Expand Down Expand Up @@ -201,7 +198,8 @@ header type
2drop
;

create scratch 0 ,
: var: r> ; \ variable defining word

header base :noname var: create base $a ,
header state :noname var: create state 0 ,
header >in :noname var: create >in 0 ,
Expand All @@ -217,7 +215,7 @@ create fineforoptimisation 0 ,
create tib #128 allot

: nextword
@ h# 7ffe and
@ d# -2 and
;

header words : words
Expand Down Expand Up @@ -252,9 +250,7 @@ header words : words
\ ;

header abs : abs dup
: ?neg 0<
asm-0branch noop
negate ;
: ?neg 0< if negate then ;
header here : here dp @i ;

header /string
Expand All @@ -273,28 +269,25 @@ header aligned
;

header d+
: d+ ( al ah bl bh )
swap >r + swap ( h al )
r@ + swap ( l h )
over r> u< -
: d+ ( augend . addend . -- sum . )
rot + >r ( augend addend)
over+ ( augend sum)
tuck swap ( sum sum augend)
u< negate ( sum)
r> + ( sum . )
;

header dnegate
: dnegate
invert
swap ( ~hi lo )
negate ( ~hi -lo )
tuck ( -lo ~hi -lo )
0= -
invert swap invert swap
d# 1. d+
;

header dabs
: dabs ( d -- ud )
dup
: ?dneg ( d n -- d2 ) \ negate d if n is negative
0<
asm-0branch noop
dnegate
0< if dnegate then
;

header s>d
Expand Down Expand Up @@ -322,6 +315,8 @@ header d0=
\ begin again
\ ;

create scratch 0 ,

header d2*
: d2*
2* over d# 0 < d# 1 and + swap 2* swap
Expand Down Expand Up @@ -579,7 +574,7 @@ header parse-name
['] isnotspace?
: _parse
xt-skip ( end-word restlen r: start-word )
2dup 0<> - sourceA @i - >in!
2dup d# 1 min + sourceA @i - >in!
drop r>
tuck -
;
Expand Down Expand Up @@ -616,9 +611,7 @@ header c,

header compile,
: compile,
2/ h# 4000
: orw,
or w,
2/ h# 4000 or w,
;


Expand Down Expand Up @@ -760,7 +753,7 @@ header-imm again

header-imm until
: tuntil
h# 2000 orw, \ backward conditional
h# 2000 or w, \ backward conditional
;

header does>
Expand Down Expand Up @@ -939,22 +932,20 @@ header char+ :noname 1+ ;
header chars :noname noop ;

: jumptable ( u -- ) \ add u to the return address
r> + execute ;
r> + >r ;

header abort
: abort
[char] ? emit
d# 2 execute
;

header '
:noname
parse-name
sfind
0=
: isvoid ( caddr u -- ) \ any char remains, abort
nip
: ?abort
asm-0branch noop
abort
if
abort
then
;

: consume1 ( caddr u ch -- caddr' u' f )
Expand All @@ -963,16 +954,20 @@ header '
dup>r negate /string r>
;

create signflag 0 ,

: ((doubleAlso))
h# 0. 2swap
[char] - consume1 signflag _!
[char] - consume1 >r
>number
[char] . consume1 >r \ 0 is single, -1 double
nip ?abort \ any chars remain: abort
signflag @i ?dneg \ is negative
r> ?dup and \ if single, remove high cell
[char] . consume1 if
isvoid \ double number
r> ?dneg
d# 2 exit
then
\ single number
isvoid drop
r> ?neg
: return1
d# 1
;

: base((doubleAlso))
Expand All @@ -991,7 +986,7 @@ create signflag 0 ,
swap d# 2 + is'
;

\ (doubleAlso) ( c-addr u -- x 0 | x x 1 )
\ (doubleAlso) ( c-addr u -- x 1 | x x 2 )
\ If the string is legal, give a single or double cell number
\ and size of the number.

Expand All @@ -1006,7 +1001,7 @@ create signflag 0 ,
d# 2 base((doubleAlso)) ;
then
2dup is'c' if
drop 1+ c@ false ;
drop 1+ c@ return1 ;
then
((doubleAlso))
;
Expand All @@ -1021,7 +1016,7 @@ header-imm literal
invert tliteral
inline: invert
else
h# 8000 orw,
h# 8000 or w,
then
;

Expand All @@ -1036,14 +1031,21 @@ header-imm postpone
compile,
;

header '
:noname
parse-name
sfind
0= ?abort
;

header char
:noname
parse-name drop c@
;

: doubleAlso,
(doubleAlso)
if
1- if
swap tliteral
then
tliteral
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10 changes: 5 additions & 5 deletions j1a/swapforth.fs
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Expand Up @@ -39,16 +39,16 @@
postpone then
; immediate

: >body
4 +
;

: create
:
here >body postpone literal
here 4 + postpone literal
postpone ;
;

: >body
@ 32767 and
;

include core.fs

: /mod >r s>d r> sm/rem ;
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12 changes: 7 additions & 5 deletions j1a/verilator/vsim.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -126,11 +126,13 @@ static void cycle(v3* v)
dut->clk = 1;
dut->eval();

int pc = 4095 & dut->v__DOT___j1__DOT__pc;
if (dut->v__DOT___j1__DOT__dstack__DOT__depth > v->ddepth[pc])
v->ddepth[pc] = dut->v__DOT___j1__DOT__dstack__DOT__depth;
if (dut->v__DOT___j1__DOT__rstack__DOT__depth > v->rdepth[pc])
v->rdepth[pc] = dut->v__DOT___j1__DOT__rstack__DOT__depth;
int pc = dut->v__DOT___j1__DOT__pc;
if (pc < 4096) {
if (dut->v__DOT___j1__DOT__dstack__DOT__depth > v->ddepth[pc])
v->ddepth[pc] = dut->v__DOT___j1__DOT__dstack__DOT__depth;
if (dut->v__DOT___j1__DOT__rstack__DOT__depth > v->rdepth[pc])
v->rdepth[pc] = dut->v__DOT___j1__DOT__rstack__DOT__depth;
}
}

PyObject *v3_read(PyObject *_, PyObject *args)
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12 changes: 7 additions & 5 deletions j1a/verilog/j1.v
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ module j1(
output wire [12:0] code_addr,
input wire [15:0] insn);

reg [3:0] dsp, dspN; // data stack pointer
reg [4:0] dsp, dspN; // data stack pointer
reg [`WIDTH-1:0] st0, st0N; // top of data stack
reg dstkW; // data stack write

Expand All @@ -32,8 +32,10 @@ module j1(
// The D and R stacks
wire [`WIDTH-1:0] st1, rst0;
reg [1:0] dspI, rspI;
stack2 #(.DEPTH(15)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
stack2 #(.DEPTH(17)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
stack2 #(.DEPTH(16)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
stack2 #(.DEPTH(19)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
// stack2 #(.DEPTH(24)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
// stack2 #(.DEPTH(24)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));

wire [16:0] minus = {1'b1, ~st0} + st1 + 1;
wire signedless = st0[15] ^ st1[15] ? st1[15] : minus[16];
Expand Down Expand Up @@ -63,7 +65,7 @@ module j1(
9'b0_011_?1011: st0N = rst0;
9'b0_011_?1100: st0N = minus[15:0];
9'b0_011_?1101: st0N = io_din;
9'b0_011_?1110: st0N = {{(`WIDTH - 4){1'b0}}, dsp};
9'b0_011_?1110: st0N = {{(`WIDTH - 5){1'b0}}, dsp};
9'b0_011_?1111: st0N = {`WIDTH{(minus[16])}}; // u<
default: st0N = {`WIDTH{1'bx}};
endcase
Expand Down Expand Up @@ -92,7 +94,7 @@ module j1(
4'b0_011: {dstkW, dspI} = {func_T_N, {insn[1:0]}};
default: {dstkW, dspI} = {1'b0, 2'b00};
endcase
dspN = dsp + {dspI[1], dspI[1], dspI};
dspN = dsp + {dspI[1], dspI[1], dspI[1], dspI};

casez ({pc[12], insn[15:13]})
4'b1_???: {rstkW, rspI} = {1'b0, 2'b11};
Expand Down

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