LaCrosse mode 1 optimization register settings #1022
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SD_ProtocolData.pm Reg. 0x02 - IOCFG0 0x2E, GDO0 output pin configuration High impedance (3-state) - unused in FSK-modes Reg. 0x03 - FIFOTHR 0x41, Design Note DN009, FIFOTHR.ADC_RETENTION - CC1101 will wake up with optimal ADC settings for low data rate (≤ 100 kbps) Reg. 0x06 - PKTLEN 0x05 (5 Byte) Reg. 0x07 - PKTCTRL1 0x80, Preamble quality estimator threshold (2 Byte) Reg. 0x08 - PKTCTRL0 0x00, Fixed packet length mode. Length configured in PKTLEN register Reg. 0x12 - MDMCFG2 0x02, SYNC_MODE 16/16 sync word bits detected
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@@ Coverage Diff @@
## master #1022 +/- ##
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- Coverage 50.03% 50.01% -0.02%
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Files 218 218
Lines 15279 15274 -5
Branches 2859 2859
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- Hits 7645 7640 -5
Misses 5995 5995
Partials 1639 1639
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sidey79
approved these changes
Oct 4, 2021
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What is the current behavior?
(You can also link to an open issue here, if this describes the current behavior)
GDO0 is defined as an output.
Interrupt is only given in the FIFOTHR register specified number of bytes triggered (can only be set in steps of 4 bytes).
16/16 + carrier-sense above threshold
What is the new behavior (if this is a feature change)?
GDO0 output pin configuration, High impedance (3-state) - unused in FSK-modes
CC1101 will wake up with optimal ADC settings for low data rate (≤ 100 kbps)
The interrupt is triggered when the number of bytes required by the message is reached.
SYNC_MODE 16/16 sync word bits detected
Does this PR introduce a breaking change? (What changes might users need to make in their application due to this PR?)
no
Other information: