Skip to content

Commit

Permalink
drm/i915: Make sandybridge_pcode_read() deal with the second data reg…
Browse files Browse the repository at this point in the history 
…ister

The pcode mailbox has two data registers. So far we've only ever used
the one, but that's about to change. Expose the second data register to
the callers of sandybridge_pcode_read().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190521164025.30225-1-ville.syrjala@linux.intel.com
  • Loading branch information
@vsyrjala
vsyrjala committed May 27, 2019
1 parent 4361cca commit d284d51
Show file tree
Hide file tree
Showing 4 changed files with 20 additions and 14 deletions.
4 changes: 2 additions & 2 deletions drivers/gpu/drm/i915/i915_debugfs.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1500,7 +1500,7 @@ static int gen6_drpc_info(struct seq_file *m)

if (INTEL_GEN(dev_priv) <= 7)
sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
&rc6vids);
&rc6vids, NULL);

seq_printf(m, "RC1e Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
Expand Down Expand Up @@ -1783,7 +1783,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
ia_freq = gpu_freq;
sandybridge_pcode_read(dev_priv,
GEN6_PCODE_READ_MIN_FREQ_TABLE,
&ia_freq);
&ia_freq, NULL);
seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
intel_gpu_freq(dev_priv, (gpu_freq *
(IS_GEN9_BC(dev_priv) ||
Expand Down
12 changes: 7 additions & 5 deletions drivers/gpu/drm/i915/intel_pm.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2822,7 +2822,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
val = 0; /* data0 to be programmed to 0 for first set */
ret = sandybridge_pcode_read(dev_priv,
GEN9_PCODE_READ_MEM_LATENCY,
&val);
&val, NULL);

if (ret) {
DRM_ERROR("SKL Mailbox read error = %d\n", ret);
Expand All @@ -2841,7 +2841,7 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
val = 1; /* data0 to be programmed to 1 for second set */
ret = sandybridge_pcode_read(dev_priv,
GEN9_PCODE_READ_MEM_LATENCY,
&val);
&val, NULL);
if (ret) {
DRM_ERROR("SKL Mailbox read error = %d\n", ret);
return;
Expand Down Expand Up @@ -7072,7 +7072,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)

if (sandybridge_pcode_read(dev_priv,
HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
&ddcc_status) == 0)
&ddcc_status, NULL) == 0)
rps->efficient_freq =
clamp_t(u8,
((ddcc_status >> 8) & 0xff),
Expand Down Expand Up @@ -7419,7 +7419,8 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
GEN6_RC_CTL_HW_ENABLE);

rc6vids = 0;
ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
&rc6vids, NULL);
if (IS_GEN(dev_priv, 6) && ret) {
DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
} else if (IS_GEN(dev_priv, 6) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
Expand Down Expand Up @@ -8566,7 +8567,8 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
u32 params = 0;

sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS,
&params, NULL);
if (params & BIT(31)) { /* OC supported */
DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
(rps->max_freq & 0xff) * 50,
Expand Down
15 changes: 9 additions & 6 deletions drivers/gpu/drm/i915/intel_sideband.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -374,7 +374,7 @@ static inline int gen7_check_mailbox_status(u32 mbox)
}

static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
u32 mbox, u32 *val,
u32 mbox, u32 *val, u32 *val1,
int fast_timeout_us,
int slow_timeout_ms,
bool is_read)
Expand All @@ -393,7 +393,7 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
return -EAGAIN;

intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, 0);
intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, val1 ? *val1 : 0);
intel_uncore_write_fw(uncore,
GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);

Expand All @@ -407,19 +407,22 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,

if (is_read)
*val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA);
if (is_read && val1)
*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);

if (INTEL_GEN(i915) > 6)
return gen7_check_mailbox_status(mbox);
else
return gen6_check_mailbox_status(mbox);
}

int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val)
int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
u32 *val, u32 *val1)
{
int err;

mutex_lock(&i915->sb_lock);
err = __sandybridge_pcode_rw(i915, mbox, val,
err = __sandybridge_pcode_rw(i915, mbox, val, val1,
500, 0,
true);
mutex_unlock(&i915->sb_lock);
Expand All @@ -440,7 +443,7 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
int err;

mutex_lock(&i915->sb_lock);
err = __sandybridge_pcode_rw(i915, mbox, &val,
err = __sandybridge_pcode_rw(i915, mbox, &val, NULL,
fast_timeout_us, slow_timeout_ms,
false);
mutex_unlock(&i915->sb_lock);
Expand All @@ -457,7 +460,7 @@ static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
u32 request, u32 reply_mask, u32 reply,
u32 *status)
{
*status = __sandybridge_pcode_rw(i915, mbox, &request,
*status = __sandybridge_pcode_rw(i915, mbox, &request, NULL,
500, 0,
true);

Expand Down
3 changes: 2 additions & 1 deletion drivers/gpu/drm/i915/intel_sideband.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -127,7 +127,8 @@ u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
enum intel_sbi_destination destination);

int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val);
int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
u32 *val, u32 *val1);
int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
u32 val, int fast_timeout_us,
int slow_timeout_ms);
Expand Down

0 comments on commit d284d51

Please sign in to comment.