Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Add the mill wrapper (millw) #2846

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
+14 −8
Open

Add the mill wrapper (millw) #2846

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 3 additions & 0 deletions .gitmodules
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19,3 +19,6 @@
[submodule "coupledL2"]
path = coupledL2
url = https://github.com/OpenXiangShan/coupledL2
[submodule "tools/millw"]
path = tools/millw
url = https://github.com/lefou/millw.git
11 changes: 6 additions & 5 deletions Makefile
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@ IMAGE ?= temp
CONFIG ?= DefaultConfig
NUM_CORES ?= 1
MFC ?= 0
MILL ?= ./millw

# common chisel args
ifeq ($(MFC),1)
Expand Down Expand Up @@ -110,11 +111,11 @@ endif
.DEFAULT_GOAL = verilog

help:
mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help
$(MILL) -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help

$(TOP_V): $(SCALA_FILE)
mkdir -p $(@D)
$(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \
$(TIME_CMD) $(MILL) -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) \
-td $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS) \
--num-cores $(NUM_CORES) $(RELEASE_ARGS)
ifeq ($(MFC),1)
Expand All @@ -136,7 +137,7 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
mkdir -p $(@D)
@echo "\n[mill] Generating Verilog files..." > $(TIMELOG)
@date -R | tee -a $(TIMELOG)
$(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \
$(TIME_CMD) $(MILL) -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP) \
-td $(@D) --config $(CONFIG) $(SIM_MEM_ARGS) \
--num-cores $(NUM_CORES) $(SIM_ARGS)
ifeq ($(MFC),1)
Expand Down Expand Up @@ -175,10 +176,10 @@ bump:
git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master"

bsp:
mill -i mill.bsp.BSP/install
$(MILL) -i mill.bsp.BSP/install

idea:
mill -i mill.scalalib.GenIdea/idea
$(MILL) -i mill.scalalib.GenIdea/idea

# verilator simulation
emu: sim-verilog
Expand Down
6 changes: 3 additions & 3 deletions Makefile.test
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
# only generate a small module: example
verilog-decode:
mill -i XiangShan.test.runMain xiangshan.DecodeMain -td build --output-file DecodeUnit.v
$(MILL) -i XiangShan.test.runMain xiangshan.DecodeMain -td build --output-file DecodeUnit.v

# chiseltest
# autorun all the chiselTest case
test:
mill -i XiangShan.test.test
$(MILL) -i XiangShan.test.test

# only run DecodeUnitTest
test-DecodeUnit:
mill -i XiangShan.test.testOnly xiangshan.DecodeUnitTest
$(MILL) -i XiangShan.test.testOnly xiangshan.DecodeUnitTest
1 change: 1 addition & 0 deletions millw
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
tools/millw/millw
1 change: 1 addition & 0 deletions tools/millw
Open in desktop
Submodule millw added at 2254cf
Loading