How to generate verilog file for FPGA build? #1501
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I am trying to build a FPGA model, any advice how to generate the full system verilog file? |
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Answered by
poemonsense
Mar 28, 2022
Replies: 2 comments 1 reply
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We don't provide full-system Verilog file. We provide top-level with 3 AXIs. |
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1 reply
Answer selected by
kyeoh2
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Thanks for the answer. |
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We don't provide full-system Verilog file. We provide top-level with 3 AXIs.
make verilog
generates it.