Revert "fix for chipsalliance/rocket-chip#2967 (#1562)"

This reverts commit 0849364.
OpenXiangShan · Jun 28, 2022 · a234247 · a234247
1 parent 6166923
commit a234247
Show file tree

Hide file tree

Showing 9 changed files with 980 additions and 82 deletions.
diff --git a/rocket-chip b/rocket-chip
diff --git a/src/main/scala/device/RocketDebugWrapper.scala b/src/main/scala/device/RocketDebugWrapper.scala
@@ -25,11 +25,13 @@ import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.amba.apb._
 import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalModuleTree
 import freechips.rocketchip.jtag._
 import freechips.rocketchip.util._
 import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.devices.debug.{DebugCustomXbar, DebugIO, DebugTransportModuleJTAG, JtagDTMConfig, PSDIO, ResetCtrlIO, SystemJTAGIO, TLDebugModule}
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.GenericLogicalTreeNode
 import freechips.rocketchip.devices.debug._
 
 // this file uses code from rocketchip Periphery.scala
@@ -48,6 +50,8 @@ class DebugModule(numCores: Int)(implicit p: Parameters) extends LazyModule {
 //  debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
 //    l2xbar := TLBuffer() := TLWidthWidget(1) := sb2tl.node
 //  }
+  val fakeTreeNode = new GenericLogicalTreeNode
+  LogicalModuleTree.add(fakeTreeNode, debug.logicalTreeNode)
 
   lazy val module = new LazyRawModuleImp(this) {
     val io = IO(new Bundle{

diff --git a/src/main/scala/top/Top.scala b/src/main/scala/top/Top.scala
@@ -29,6 +29,7 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.GenericLogicalTreeNode
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.jtag.JTAGIO
 import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen}

diff --git a/src/main/scala/xiangshan/XSTile.scala b/src/main/scala/xiangshan/XSTile.scala
@@ -4,6 +4,7 @@ import chisel3._
 import chipsalliance.rocketchip.config.{Config, Parameters}
 import chisel3.util.{Valid, ValidIO}
 import freechips.rocketchip.diplomacy.{BundleBridgeSink, LazyModule, LazyModuleImp, LazyModuleImpLike}
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.GenericLogicalTreeNode
 import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortParameters, IntSinkPortSimple}
 import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
 import freechips.rocketchip.tilelink.{BankBinder, TLBuffer, TLIdentityNode, TLNode, TLTempNode, TLXbar}
@@ -42,7 +43,7 @@ class XSTileMisc()(implicit p: Parameters) extends LazyModule
   val mmio_port = TLIdentityNode() // to L3
   val memory_port = TLIdentityNode()
   val beu = LazyModule(new BusErrorUnit(
-    new XSL1BusErrors(), BusErrorUnitParams(0x38010000)
+    new XSL1BusErrors(), BusErrorUnitParams(0x38010000), new GenericLogicalTreeNode
   ))
   val busPMU = BusPerfMonitor(enable = !debugOpts.FPGAPlatform)
   val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", !debugOpts.FPGAPlatform)

diff --git a/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala b/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
diff --git a/src/main/scala/xiangshan/backend/decode/FPDecoder.scala b/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
@@ -20,7 +20,7 @@ import chipsalliance.rocketchip.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.rocket.DecodeLogic
-import freechips.rocketchip.rocket.Instructions._
+import xiangshan.backend.decode.Instructions._
 import xiangshan.backend.fu.fpu.FPU
 import xiangshan.{FPUCtrlSignals, XSModule}
 

diff --git a/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala b/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
@@ -18,10 +18,10 @@ package xiangshan.backend.decode
 
 import chipsalliance.rocketchip.config.Parameters
 import chisel3._
+import chisel3.util.BitPat.bitPatToUInt
 import chisel3.util._
-import freechips.rocketchip.rocket.Instructions
-import utils._
 import xiangshan._
+import utils._
 
 abstract class BaseFusionCase(pair: Seq[Valid[UInt]])(implicit p: Parameters)
   extends DecodeUnitConstants {
@@ -89,7 +89,7 @@ class FusedAdduw(pair: Seq[Valid[UInt]])(implicit p: Parameters) extends BaseFus
 
   def isValid: Bool = inst1Cond && inst2Cond && withSameDest && destToRs1
   override def thisInstr: Option[BitPat] = Some(Instructions.SLLI)
-  override def fusedInstr: Option[BitPat] = Some(Instructions.ADD_UW)
+  override def fusedInstr: Option[BitPat] = Some(Instructions.ADDU_W)
   override def lsrc2NeedZero: Boolean = true
 
   def fusionName: String = "slli32_srli32"

diff --git a/src/main/scala/xiangshan/backend/decode/Instructions.scala b/src/main/scala/xiangshan/backend/decode/Instructions.scala
diff --git a/src/main/scala/xiangshan/package.scala b/src/main/scala/xiangshan/package.scala
@@ -118,7 +118,6 @@ package object xiangshan {
 
   object FuOpType {
     def apply() = UInt(7.W)
-    def X = BitPat("b???????")
   }
 
   object CommitType {