Makefile,difftest: Support palladium simulation (#2662)

Makefile

@@ -82,7 +82,7 @@ endif
 # emu for the release version
 RELEASE_ARGS += --disable-all --remove-assert --fpga-platform
 DEBUG_ARGS   += --enable-difftest
-PLDM_ARGS += --disable-all --fpga-platform
+PLDM_ARGS += --disable-all --fpga-platform --enable-difftest
 ifeq ($(RELEASE),1)
 override SIM_ARGS += $(RELEASE_ARGS)
 else ifeq ($(PLDM),1)
@@ -96,6 +96,11 @@ TIME_CMD = time -a -o $(TIMELOG)
 
 SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g'
 
+ifeq ($(PLDM),1)
+SED_IFNDEF = `ifndef SYNTHESIS	// src/main/scala/device/RocketDebugWrapper.scala
+SED_ENDIF  = `endif // not def SYNTHESIS
+endif
+
 .DEFAULT_GOAL = verilog
 
 help:
@@ -142,7 +147,7 @@ endif
 	@rm .__head__ .__diff__
 ifeq ($(PLDM),1)
 	sed -i -e 's/$$fatal/$$finish/g' $(SIM_TOP_V)
-	sed -i -e 's|`ifndef SYNTHESIS	// src/main/scala/device/RocketDebugWrapper.scala:141:11|`ifdef SYNTHESIS	// src/main/scala/device/RocketDebugWrapper.scala:141:11|g' $(SIM_TOP_V)
+	sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(SIM_TOP_V)
 else
 	sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V)
 endif
@@ -180,6 +185,16 @@ emu-run: emu
 simv:
 	$(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
 
+# palladium simulation
+pldm-build: sim-verilog
+	$(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
+
+pldm-run:
+	$(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
+
+pldm-debug:
+	$(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
+
 include Makefile.test
 
 .PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO)