Enable paging for 64-bit vexpress #1575

jenswi-linaro · 2017-06-01T19:07:50Z

No description provided.

jenswi-linaro · 2017-06-05T08:25:22Z

Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno AArch64)

jenswi-linaro · 2017-06-12T13:13:53Z

Adds a fix for OP-TEE/optee_test#216

jforissier · 2017-06-12T15:12:02Z

Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Hikey GP)

Tested with #1592 and OP-TEE/optee_test#216.

etienne-lms

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
commit01 "core: assert against recursive mutex locking"
commit02 "core: REE_FS: avoid deadlock in ree_fs_create()"
commit03 "ltc: fix 64-bit warning"
commit04 (minor comments) "core: make 64-bit tlb invalidation inner shareable"
commit05 "core: add dsb instructions for tlb invalidation"
commit08 "core: update 64-bit copy_init from 32-bit version"
commit09 "core: arm: increase emulated SRAM"
commit10 "plat-vexpress: enable 64-bit paging"
commit11 "travis: compile QEMU v8 with CFG_WITH_PAGER=y"
commit12 (minor comment ) "core: bugfix tee_pager_release_phys()"

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
commit06 "core: link script: .bss alignment"
commit07 "core: 64-bit update release_unused_kernel_stack()"

etienne-lms · 2017-06-13T09:32:07Z

core/arch/arm/mm/tee_pager.c

@@ -1403,6 +1406,8 @@ static void pager_save_and_release_entry(struct tee_pager_pmem *pmem)

 	area_get_entry(pmem->area, pmem->pgidx, NULL, &attr);
 	area_set_entry(pmem->area, pmem->pgidx, 0, 0);
+	/* TODO only invalidate entry touched above */
+	core_tlb_maintenance(TLBINV_UNIFIEDTLB, 0);


~~in tee_pager_release_one_phys(), there may also need a tlb invalidation.~~
edited: discard my comment, TLB maintenance is already implemented from tee_pager_release_phys() once all target pages where released.

Yes, I noticed that too. :-)

etienne-lms · 2017-06-13T09:56:34Z

core/arch/arm/kernel/ssvce_a32.S

@@ -55,6 +55,7 @@
 FUNC secure_mmu_unifiedtlbinvall , :
 UNWIND(	.fnstart)

+	dsb	/* Ensure visibility of the update to translation table walks */


Can use dsb ishst here and dsb ish below after tlbi invalidation. ARMv7 support these.

This can apply to modified secure_mmu_unifiedtlbinvXXX() below.
(Yet this could come in a later patch, I am preparing something to invalidate by mva when necessary)

Yes, I'd rather take that in a later patch.

Adds an assert to check that the thread holding a mutex tries to lock it again. Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

ree_fs_close() can't be called in ree_fs_create() cleanup as ree_fs_close() tries to acquire the mutex already acquired in ree_fs_create(). Copy relevant content from ree_fs_close() instead. Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

Adds DSB instructions needed for correct visibility of TLB invalidations. Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

jenswi-linaro · 2017-06-13T11:44:42Z

Rebased, tags applied. Note that "core: pager: invalidate tlb when clearing entry" doesn't have an R-B tag, but I not sure it matters much.

jforissier · 2017-06-13T11:49:37Z

Note that "core: pager: invalidate tlb when clearing entry" doesn't have an R-B tag, but I not sure it matters much

It's OK with me. Could you mention that it fixes xtest 1016, maybe?

When clearing an entry in a translation table corresponding TLB entry must always be invalidated. With this patch two missing places are addressed. This fixes problem in xtest regression suite case 1016. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

.bss may need a larger alignment than 8. Instead of trying to guess let the linker chose it and to avoid having an unaccounted hole before .bss set __data_end first thing inside the .bss section. This makes sure that the data section is properly padded out when assembling a paged tee.bin. Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

Fixes the case where less than a page is to be released by ignoring the request. Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

release_unused_kernel_stack() is called when the pager is enabled when the state of a thread is saved in order to release unused stack pages. Update release_unused_kernel_stack() for 64-bit mode. Acked-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

Updates the copy_init part in generic_entry_a64.S from generic_entry_a32.S Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

Increases emulated TrustZone protected SRAM to 448 kB to increase the pager performance especially for 64-bit mode. Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Hikey GP) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (Juno AArch64) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP AArch64) Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU AArch64) Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

jenswi-linaro · 2017-06-13T12:14:44Z

Commit message in "core: pager: invalidate tlb when clearing entry" updated.

jforissier · 2017-06-13T14:01:39Z

Merged, thanks. Travis failure is due to the build exceeding the time limit.

kenlsoft · 2017-06-14T02:50:06Z

Hello Jenswi,
May I ask which platform are you tested ? Seems my platform could not hold even pager part for current.

jenswi-linaro · 2017-06-14T06:19:28Z

QEMU-Virt-ARMv8, Fast Models Foundation model, Juno.
@jforissier has also tested on Hikey with #1592 rebased on top
If you look through the commits in this PR and also #1598 you'll notice that certain modification has been done related to the amount of (emulated) SRAM.

jenswi-linaro force-pushed the pager64 branch from 33dbe9e to c5dada5 Compare June 12, 2017 13:55

jforissier mentioned this pull request Jun 12, 2017

plat-hikey: enable 64-bit paging #1592

Merged

etienne-lms reviewed Jun 13, 2017

View reviewed changes

jenswi-linaro added 5 commits June 13, 2017 13:28

core: assert against recursive mutex locking

439afae

Adds an assert to check that the thread holding a mutex tries to lock it again. Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

ltc: fix 64-bit warning

8df3474

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: make 64-bit tlb invalidation inner shareable

7c74bb3

Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: add dsb instructions for tlb invalidation

159efbc

Adds DSB instructions needed for correct visibility of TLB invalidations. Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

jenswi-linaro force-pushed the pager64 branch from c5dada5 to caa0138 Compare June 13, 2017 11:42

jenswi-linaro added 8 commits June 13, 2017 14:13

core: bugfix tee_pager_release_phys()

7fd107a

Fixes the case where less than a page is to be released by ignoring the request. Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: update 64-bit copy_init from 32-bit version

f2bdb6d

Updates the copy_init part in generic_entry_a64.S from generic_entry_a32.S Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core: arm: increase emulated SRAM

7c930be

Increases emulated TrustZone protected SRAM to 448 kB to increase the pager performance especially for 64-bit mode. Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

travis: compile QEMU v8 with CFG_WITH_PAGER=y

ff3799d

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

jenswi-linaro force-pushed the pager64 branch from caa0138 to ff3799d Compare June 13, 2017 12:14

jforissier merged commit fe8f79d into OP-TEE:master Jun 13, 2017

jenswi-linaro deleted the pager64 branch June 13, 2017 17:49

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Enable paging for 64-bit vexpress #1575

Enable paging for 64-bit vexpress #1575

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Enable paging for 64-bit vexpress #1575

Enable paging for 64-bit vexpress #1575

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