plat-ls: Add support for armv8 platform flavours

Added support for armv8 platform flavours as follows:
- PLATFORM = ls-ls1043ardb
- PLATFORM = ls-ls1046ardb

Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

.travis.yml

@@ -216,10 +216,16 @@ script:
   - $make PLATFORM=sprd-sc9860
   - $make PLATFORM=sprd-sc9860 CFG_ARM64_core=y
 
-  # FSL ls1021a
+  # NXP LS1021A
   - $make PLATFORM=ls-ls1021atwr
   - $make PLATFORM=ls-ls1021aqds
 
+  # NXP LS1043A-RDB (ARMv8-A)
+  - $make PLATFORM=ls-ls1043ardb CFG_ARM64_core=y
+
+  # NXP LS1046A-RDB (ARMv8-A)
+  - $make PLATFORM=ls-ls1046ardb CFG_ARM64_core=y
+
   # Xilinx Zynq7000 ZC702
   - $make PLATFORM=zynq7k-zc702
 

MAINTAINERS.md

@@ -10,7 +10,9 @@ for these platforms.
 | Allwinner A80 Board			|`Sun Yangbang <sunny@allwinnertech.com>`|
 | ARM Juno Board			|`Linaro <op-tee@linaro.org>`|
 | Atmel ATSAMA5D2-XULT Board		|`Akshay Bhat <akshay.bhat@timesys.com>`|
-| FSL ls1021a				|`Sumit Garg <sumit.garg@freescale.com>`|
+| NXP LS1021A				|`Sumit Garg <sumit.garg@nxp.com>`|
+| NXP LS1043A-RDB			|`Sumit Garg <sumit.garg@nxp.com>`|
+| NXP LS1046A-RDB			|`Sumit Garg <sumit.garg@nxp.com>`|
 | FSL i.MX6 Quad SABRE Lite Board	|`Yan Yan <yan.yan@windriver.com>`,`Feng Yu <Yu.Feng@windriver.com>`|
 | FSL i.MX6 Quad SABRE SD Board		|`Yan Yan <yan.yan@windriver.com>`,`Feng Yu <Yu.Feng@windriver.com>`|
 | FSL i.MX6 UltraLite EVK Board		|`Peng Fan <peng.fan@nxp.com>`|

README.md

@@ -48,6 +48,8 @@ platforms have different sub-maintainers, please refer to the file
 | [ARM Juno Board](http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php) |`PLATFORM=vexpress-juno`| Yes |
 | [Atmel ATSAMA5D2-XULT Board](http://www.atmel.com/tools/atsama5d2-xult.aspx)|`PLATFORM=sam`| Yes |
 | [FSL ls1021a](http://www.freescale.com/tools/embedded-software-and-tools/hardware-development-tools/tower-development-boards/mcu-and-processor-modules/powerquicc-and-qoriq-modules/qoriq-ls1021a-tower-system-module:TWR-LS1021A?lang_cd=en)|`PLATFORM=ls-ls1021atwr`| Yes |
+| [NXP ls1043ardb](http://www.nxp.com/products/microcontrollers-and-processors/power-architecture-processors/qoriq-platforms/developer-resources/qoriq-ls1043a-reference-design-board:LS1043A-RDB)|`PLATFORM=ls-ls1043ardb`| Yes |
+| [NXP ls1046ardb](http://www.nxp.com/products/microcontrollers-and-processors/power-architecture-processors/qoriq-platforms/developer-resources/qoriq-ls1046a-reference-design-board:LS1046A-RDB)|`PLATFORM=ls-ls1046ardb`| Yes |
 | [FSL i.MX6 Quad SABRE Lite Board](https://boundarydevices.com/product/sabre-lite-imx6-sbc/) |`PLATFORM=imx-mx6qsabrelite`| Yes |
 | [FSL i.MX6 Quad SABRE SD Board](http://www.nxp.com/products/software-and-tools/hardware-development-tools/sabre-development-system/sabre-board-for-smart-devices-based-on-the-i.mx-6quad-applications-processors:RD-IMX6Q-SABRE) |`PLATFORM=imx-mx6qsabresd`| Yes |
 | [FSL i.MX6 UltraLite EVK Board](http://www.freescale.com/products/arm-processors/i.mx-applications-processors-based-on-arm-cores/i.mx-6-processors/i.mx6qp/i.mx6ultralite-evaluation-kit:MCIMX6UL-EVK) |`PLATFORM=imx-mx6ulevk`| Yes |

core/arch/arm/plat-ls/conf.mk

@@ -1,19 +1,45 @@
 PLATFORM_FLAVOR ?= ls1021atwr
 
-include core/arch/arm/cpu/cortex-a7.mk
-
 core_arm32-platform-aflags	+= -mfpu=neon
 
 $(call force,CFG_GENERIC_BOOT,y)
-$(call force,CFG_ARM32_core,y)
 $(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
 $(call force,CFG_GIC,y)
 $(call force,CFG_16550_UART,y)
 $(call force,CFG_PM_STUBS,y)
 
-ta-targets = ta_arm32
+ifeq ($(PLATFORM_FLAVOR),ls1021atwr)
+include core/arch/arm/cpu/cortex-a7.mk
+CFG_BOOT_SYNC_CPU ?= y
+CFG_BOOT_SECONDARY_REQUEST ?= y
+endif
 
+ifeq ($(PLATFORM_FLAVOR),ls1021aqds)
+include core/arch/arm/cpu/cortex-a7.mk
 CFG_BOOT_SYNC_CPU ?= y
 CFG_BOOT_SECONDARY_REQUEST ?= y
+endif
+
+ifeq ($(PLATFORM_FLAVOR),ls1043ardb)
+include core/arch/arm/cpu/cortex-armv8-0.mk
+endif
+
+ifeq ($(PLATFORM_FLAVOR),ls1046ardb)
+include core/arch/arm/cpu/cortex-armv8-0.mk
+endif
+
+ifeq ($(platform-flavor-armv8),1)
+$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
+endif
+
+ta-targets = ta_arm32
+
+ifeq ($(CFG_ARM64_core),y)
+$(call force,CFG_WITH_LPAE,y)
+ta-targets = ta_arm64
+else
+$(call force,CFG_ARM32_core,y)
+endif
+
 CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
 CFG_WITH_STACK_CANARIES ?= y

core/arch/arm/plat-ls/ls_core_pos_a64.S

@@ -0,0 +1,36 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <asm.S>
+#include <arm.h>
+
+/* Layerscape platform specific function to calculate core position. */
+FUNC get_core_pos , :
+	mrs	x0, mpidr_el1
+	and	x0, x0, #MPIDR_CPU_MASK
+	ret
+END_FUNC get_core_pos

core/arch/arm/plat-ls/main.c

@@ -27,7 +27,7 @@
 
 #include <platform_config.h>
 
-#include <arm32.h>
+#include <arm.h>
 #include <console.h>
 #include <drivers/gic.h>
 #include <drivers/ns16550.h>
@@ -49,12 +49,21 @@ static const struct thread_handlers handlers = {
 	.std_smc = tee_entry_std,
 	.fast_smc = tee_entry_fast,
 	.nintr = main_fiq,
+#if defined(CFG_WITH_ARM_TRUSTED_FW)
+	.cpu_on = cpu_on_handler,
+	.cpu_off = pm_do_nothing,
+	.cpu_suspend = pm_do_nothing,
+	.cpu_resume = pm_do_nothing,
+	.system_off = pm_do_nothing,
+	.system_reset = pm_do_nothing,
+#else
 	.cpu_on = pm_panic,
 	.cpu_off = pm_panic,
 	.cpu_suspend = pm_panic,
 	.cpu_resume = pm_panic,
 	.system_off = pm_panic,
 	.system_reset = pm_panic,
+#endif
 };
 
 static struct gic_data gic_data;
@@ -73,6 +82,7 @@ static void main_fiq(void)
 	panic();
 }
 
+#ifdef CFG_ARM32_core
 void plat_cpu_reset_late(void)
 {
 	static uint32_t cntfrq;
@@ -120,6 +130,7 @@ void plat_cpu_reset_late(void)
 		write_cntfrq(cntfrq);
 	}
 }
+#endif
 
 void console_init(void)
 {

core/arch/arm/plat-ls/platform_config.h

@@ -63,30 +63,36 @@
 #define CONSOLE_UART_BASE		UART0_BASE
 
 #define DRAM0_BASE			0x80000000
+
+/* Platform specific defines */
+
 #if defined(PLATFORM_FLAVOR_ls1021aqds)
 #define DRAM0_SIZE			0x80000000
+#define CFG_DDR_TEETZ_RESERVED_START	0xFC000000
+#define CFG_DDR_TEETZ_RESERVED_SIZE	0x03F00000
+#define CFG_TEE_RAM_VA_SIZE		(1024 * 1024)
+#define CFG_PUB_RAM_SIZE		(1024 * 1024)
+#define CFG_TEE_CORE_NB_CORE		2
 #endif
 
 #if defined(PLATFORM_FLAVOR_ls1021atwr)
 #define DRAM0_SIZE			0x40000000
-#endif
-
-/* Location of trusted dram on layerscape */
-
-#if defined(PLATFORM_FLAVOR_ls1021atwr)
 #define CFG_DDR_TEETZ_RESERVED_START	0xBC000000
+#define CFG_DDR_TEETZ_RESERVED_SIZE	0x03F00000
+#define CFG_TEE_RAM_VA_SIZE		(1024 * 1024)
+#define CFG_PUB_RAM_SIZE		(1024 * 1024)
+#define CFG_TEE_CORE_NB_CORE		2
 #endif
 
-#if defined(PLATFORM_FLAVOR_ls1021aqds)
+#if defined(PLATFORM_FLAVOR_ls1043ardb) || defined(PLATFORM_FLAVOR_ls1046ardb)
+#define DRAM0_SIZE			0x80000000
 #define CFG_DDR_TEETZ_RESERVED_START	0xFC000000
+#define CFG_DDR_TEETZ_RESERVED_SIZE	0x04000000
+#define CFG_TEE_RAM_VA_SIZE		(2 * 1024 * 1024)
+#define CFG_PUB_RAM_SIZE		(2 * 1024 * 1024)
+#define CFG_TEE_CORE_NB_CORE		4
 #endif
 
-#define CFG_DDR_TEETZ_RESERVED_SIZE	0x03F00000
-
-#define CFG_TEE_RAM_VA_SIZE		(1024 * 1024)
-
-#define CFG_TEE_CORE_NB_CORE		2
-
 #define DDR_PHYS_START			DRAM0_BASE
 #define DDR_SIZE			DRAM0_SIZE
 
@@ -124,8 +130,7 @@
 #endif
 
 /* Full GlobalPlatform test suite requires CFG_SHMEM_SIZE to be at least 2MB */
-#define CFG_PUB_RAM_SIZE		(1 * 1024 * 1024)
-#define CFG_TEE_RAM_PH_SIZE		(1 * 1024 * 1024)
+#define CFG_TEE_RAM_PH_SIZE		CFG_TEE_RAM_VA_SIZE
 #define CFG_TA_RAM_SIZE			(CFG_DDR_TEETZ_RESERVED_SIZE - \
 					 CFG_TEE_RAM_PH_SIZE - CFG_PUB_RAM_SIZE)
 

core/arch/arm/plat-ls/sub.mk

@@ -1,4 +1,5 @@
 global-incdirs-y += .
 srcs-y += main.c
-srcs-y += ls_core_pos.S
-srcs-y += plat_init.S
+srcs-$(CFG_ARM32_core) += ls_core_pos_a32.S
+srcs-$(CFG_ARM64_core) += ls_core_pos_a64.S
+srcs-$(CFG_ARM32_core) += plat_init.S