Correct padding for SFT input data to account for sequence parallel + TE's fp8 op dimension requirements #8240
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…ing sequences to ensure divisibility by 8/16 for TE with fp8 Signed-off-by: Valerie Sarge <vsarge@nvidia.com>
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yaoyu-33
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Jan 31, 2024
… TE's fp8 op dimension requirements (#8240) * Alter GPTSFTDataset / GPTSFTPackedDataset to account for SP when padding sequences to ensure divisibility by 8/16 for TE with fp8 Signed-off-by: Valerie Sarge <vsarge@nvidia.com> * [pre-commit.ci] auto fixes from pre-commit.com hooks for more information, see https://pre-commit.ci --------- Signed-off-by: Valerie Sarge <vsarge@nvidia.com> Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
stevehuang52
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Jan 31, 2024
… TE's fp8 op dimension requirements (#8240) * Alter GPTSFTDataset / GPTSFTPackedDataset to account for SP when padding sequences to ensure divisibility by 8/16 for TE with fp8 Signed-off-by: Valerie Sarge <vsarge@nvidia.com> * [pre-commit.ci] auto fixes from pre-commit.com hooks for more information, see https://pre-commit.ci --------- Signed-off-by: Valerie Sarge <vsarge@nvidia.com> Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com> Signed-off-by: stevehuang52 <heh@nvidia.com>
ssh-meister
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Feb 15, 2024
… TE's fp8 op dimension requirements (NVIDIA#8240) * Alter GPTSFTDataset / GPTSFTPackedDataset to account for SP when padding sequences to ensure divisibility by 8/16 for TE with fp8 Signed-off-by: Valerie Sarge <vsarge@nvidia.com> * [pre-commit.ci] auto fixes from pre-commit.com hooks for more information, see https://pre-commit.ci --------- Signed-off-by: Valerie Sarge <vsarge@nvidia.com> Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com> Signed-off-by: Sasha Meister <ameister@nvidia.com>
pablo-garay
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Mar 19, 2024
… TE's fp8 op dimension requirements (#8240) * Alter GPTSFTDataset / GPTSFTPackedDataset to account for SP when padding sequences to ensure divisibility by 8/16 for TE with fp8 Signed-off-by: Valerie Sarge <vsarge@nvidia.com> * [pre-commit.ci] auto fixes from pre-commit.com hooks for more information, see https://pre-commit.ci --------- Signed-off-by: Valerie Sarge <vsarge@nvidia.com> Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com> Signed-off-by: Pablo Garay <pagaray@nvidia.com>
rohitrango
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Jun 25, 2024
… TE's fp8 op dimension requirements (NVIDIA#8240) * Alter GPTSFTDataset / GPTSFTPackedDataset to account for SP when padding sequences to ensure divisibility by 8/16 for TE with fp8 Signed-off-by: Valerie Sarge <vsarge@nvidia.com> * [pre-commit.ci] auto fixes from pre-commit.com hooks for more information, see https://pre-commit.ci --------- Signed-off-by: Valerie Sarge <vsarge@nvidia.com> Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>
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What does this PR do ?
Alters GPTSFTDataset and GPTSFTPackedDataset to pad to 8*TP when sequence parallel is enabled.
Collection: nlp/language_modeling
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