Fix and improve for OPNA #13
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Change the trigger for starting a RAM WRITE/READ sequence from CS_n to WR_n/RD_n in jt08_adpcm_drvB. Add the external input RD_n, which was omitted because it was not used until now. RD_n is only used by JT08, so I won't add it to other wrappers.
- Fix IRQ_RESET not resetting EOS properly - IRQ_RESET clear all flags including Timer-A/B - IRQ_MASK will not update when IRQ_RESET is 1 - IRQ_MASK clear masked flags
A1 is saved when selecting a register (A0=0;WRITE). When register writing (A0=1;WRITE), it is used to determine the destination register. If A1=0 when selecting a register and A1=1 when writing, the data was written to the same register with A1=0 as when selected. This case is generally a software bug. But from a hardware point of view, it is correct not to write to a register unless it is the same A1 that was selected. [Solution] When writing to a register, write data only if A1 is the same as when selected.
In the "Sound Board 2" item of the OSD, set the location to connect Sound Board 2. Expansion - Connect SB2 to the IO port of the expansion slot. Onboard - Connect SB2 to the IO port of the Onboard sound device. NOTE: Selecting "Expansion" will enable both the onboard SB1 and the expansion card's SB2. Selecting "Onboard" will enable onboard SB2 and disable SB1.
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Thank you !!!! |
theypsilon
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Aug 9, 2024
Fix and improve for OPNA
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Change PCM RAM access sequence to start with WR_n, RD_n
Fix processing of status flags added from OPNA
Improve to ignore incorrect register access caused by software bugs
Add menu to select the port to which the Sound Board 2 is connected
(for issue: Bosconian (unoffical) (19xx)(Doujin - Sth-Mai) - Sound Board II not detected #11)