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MassimoGiacobbe/README.md
  • 👋 Hi, I’m @MassimoGiacobbe
  • 👀 I’m interested in VLSI design and electronics as a whole
  • 🌱 I’m currently learning systemverilog and UVM
  • 📫 How to reach me: linkedin or email
  • 😄 Pronouns: he/him

Popular repositories Loading

  1. da_converter da_converter Public

    pwm and ppm da converters on fpga, connected to a custom nyos II processor generated via the qsys tool on quartus prime, the processor is then programmed to use the DACs both with the serial interf…

    C

  2. morse-encoder morse-encoder Public

    morse decoder developed on a custom board using STM32L496VET

    C

  3. rca_testbench rca_testbench Public

    systemverilog testbench for a simple ripple carry adder

    SystemVerilog

  4. MassimoGiacobbe MassimoGiacobbe Public

    Config files for my GitHub profile.

  5. P4_Adder_testbench P4_Adder_testbench Public

    UVM testbench for a Pentium 4 adder

    VHDL

  6. WRF_testbench WRF_testbench Public

    UVM testbench for a windowing register file

    VHDL