- 👋 Hi, I’m @MassimoGiacobbe
- 👀 I’m interested in VLSI design and electronics as a whole
- 🌱 I’m currently learning systemverilog and UVM
- 📫 How to reach me: linkedin or email
- 😄 Pronouns: he/him
Popular repositories Loading
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da_converter
da_converter Publicpwm and ppm da converters on fpga, connected to a custom nyos II processor generated via the qsys tool on quartus prime, the processor is then programmed to use the DACs both with the serial interf…
C
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rca_testbench
rca_testbench Publicsystemverilog testbench for a simple ripple carry adder
SystemVerilog
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