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update the OpenCL reference pages for v3.0.17 (#161)
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6 changes: 0 additions & 6 deletions sdk/3.0/docs/man/html/ATOMIC_VAR_INIT.html
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<a href="#_footnoteref_1">1</a>. Thus, <strong>&amp;*E</strong> is equivalent to <strong>E</strong> (even if <strong>E</strong> is a null pointer), and <strong>&amp;(E1[E2])</strong> is equivalent to <strong>E1) + (E2</strong>. It is always true that if <strong>E</strong> is an l-value that is a valid operand of the unary <strong>&amp;</strong> operator, <strong>*&amp;E</strong> is an l-value equal to <strong>E</strong>.
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<a href="#_footnoteref_2">2</a>. While the union is intended to reflect the organization of data in memory, the <strong>as_type</strong>() and <strong>as_type<em>n</em></strong>() constructs are intended to reflect the organization of data in register. The <strong>as_type</strong>() and <strong>as_type<em>n</em></strong>() constructs are intended to compile to no instructions on devices that use a shared register file designed to operate on both the operand and result types. Note that while differences in memory organization are expected to largely be limited to those arising from endianness, the register based representation may also differ due to size of the element in register. For example, an architecture may load a <code>char</code> into a 32-bit register, or a <code>char</code> vector into a SIMD vector register with fixed 32-bit element size. If the element count does not match, then the implementation should pick a data representation that most closely matches what would happen if an appropriate result type operator was applied to a register containing data of the source type. If the number of elements matches, then the <strong>as_type<em>n</em></strong>() should faithfully reproduce the behavior expected from a similar data type reinterpretation using memory/unions. So, for example if an implementation stores all single precision data as <code>double</code> in register, it should implement <strong>as_int</strong>(<code>float</code>) by first down-converting the <code>double</code> to single precision and then (if necessary) moving the single precision bits to a register suitable for operating on integer data. If data stored in different address spaces do not have the same endianness, then the &#8220;dominant endianness&#8221; of the device should prevail.
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<a href="#_footnoteref_4">4</a>. <strong>async_work_group_copy</strong> and <strong>async_work_group_strided_copy</strong> for 3-component vector types behave as <strong>async_work_group_copy</strong> and <strong>async_work_group_strided_copy</strong> respectively for 4-component vector types.
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<a href="#_footnoteref_3">3</a>. If the device address space is 64-bits, the data types <code>atomic_intptr_t</code>, <code>atomic_uintptr_t</code>, <code>atomic_size_t</code> and <code>atomic_ptrdiff_t</code> are supported if the <code>cl_khr_<wbr>int64_<wbr>base_<wbr>atomics</code> and <code>cl_khr_<wbr>int64_<wbr>extended_<wbr>atomics</code> extensions are supported and have been enabled.
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<a href="#_footnoteref_1">1</a>. This spurious failure enables implementation of compare-and-exchange on a broader class of machines, e.g. load-locked store-conditional machines.
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