net: 3snic: Add support for 3snic 3s9xx ethernet card

support 3SNIC 910/920/930 including following features:

 *1. single-root I/O virtualization (SR-IOV)
  2. virtual machine multi queue (VMMQ)
  3. receive side scaling (RSS)
  4. physical function (PF) passthrough VMs
  5. the PF promiscuous mode,unicast or multicast MAC filtering, and all multicast mode
  6. IPv4/IPv6, checksum offload,TCP Segmentation Offload (TSO), and Large Receive Offload (LRO)
  7. in-band one-click logs collection
  8. loopback tests
  9. port location indicators

product specs:

  Model   Port Config           PCIe
  3S910	  2 x 25GE SFP28	Gen3 x8
  3S920	  4 x 25GE SFP28	Gen4 x16
  3S930	  2 x 100GE QSFP28	Gen4 x16

Link: https://ramaxel.com/
Link: https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel/pulls/141
Link: https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel/pulls/159
Link: deepin-community/kernel#361
Co-developed-by: weiwei1 <weiwei1@ramaxel.com>
Signed-off-by: weiwei1 <weiwei1@ramaxel.com>
Signed-off-by: WangYuli <wangyuli@uniontech.com>

Documentation/networking/device_drivers/ethernet/3snic/sssnic.rst

@@ -0,0 +1,67 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+====================================================
+Linux Kernel Driver for 3SNIC Intelligent NIC family
+====================================================
+
+Contents
+========
+
+- `Overview`_
+- `Supported PCI vendor ID/device IDs`_
+- `Supported features`_
+- `Product specification`_
+- `Support`_
+
+Overview:
+=========
+SSSNIC is a network interface card that can meet the demand of a range
+of application scenarios,such as the Data Center Area,cloud computing
+and Financial industry,etc.
+
+The construction of SSSNIC card facilities mainly depends on servers and
+switches. 3S910, 920 and 930 are PCIe standard cards adapted to servers,
+which provide extended external business interfaces for servers.
+
+The driver supports a range of link-speed devices (100GE (40GE
+compatible) and 25GE (10GE compatible)).A negotiated and extendable
+feature set also supported.
+
+Supported PCI vendor ID/device IDs:
+===================================
+
+1f3f:9020 - SSSNIC PF
+
+Supported features:
+===================
+
+1. Support single-root I/O virtualization (SR-IOV)
+2. Support virtual machine multi queue (VMMQ)
+3. Support receive side scaling (RSS)
+4. Support physical function (PF) passthrough VMs
+5. Support the PF promiscuous mode,unicast or multicast MAC filtering, and
+all multicast mode
+6. Support IPv4/IPv6, checksum offload,TCP Segmentation Offload (TSO), and
+Large Receive Offload (LRO)
+7. Support in-band one-click logs collection
+8. Support loopback tests
+9. Support port location indicators
+
+Product specification
+=====================
+
+        ===================     ======= =============================	===============================================
+        PCI ID (pci.ids)        OEM     Product							PCIe port
+        ===================     ======= =============================	===============================================
+        1F3F:9020               3SNIC 	3S910(2 x 25GE SFP28 ports)		PCIe Gen3 x8(compatible with Gen2/ Gen1)
+        1F3F:9020               3SNIC 	3S920(4 x 25GE SFP28 ports)		PCIe Gen4 x16, compatible with Gen3/ Gen2/ Gen1
+        1F3F:9020               3SNIC 	3S930(2 x 100GE QSFP28 ports)	PCIe Gen4 x16, compatible with Gen3/ Gen2/ Gen1
+        ===================     ======= =============================	===============================================
+
+
+Support
+=======
+
+If an issue is identified with the released source code on the supported kernel
+with a supported adapter, email the specific information related to the issue to
+https://www.3snic.com.

Documentation/networking/device_drivers/ethernet/index.rst

@@ -12,6 +12,7 @@ Contents:
 
    3com/3c509
    3com/vortex
+   3snic/sssnic.rst
    amazon/ena
    altera/altera_tse
    amd/pds_core

drivers/net/ethernet/3snic/Kconfig

@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# 3SNIC network device configuration
+#
+
+config NET_VENDOR_3SNIC
+	bool "3SNIC smart NIC devices"
+	depends on PCI
+	select NET_DEVLINK
+	help
+	  If you have a network (Ethernet) card belonging to this class, say Y.
+
+	  Note that the answer to this question doesn't directly affect the
+	  kernel: saying N will just cause the configurator to skip all
+	  the questions about 3SNIC cards. If you say Y, you will be
+	  asked for your specific card in the following questions.
+
+if NET_VENDOR_3SNIC
+
+source "drivers/net/ethernet/3snic/sssnic/Kconfig"
+
+endif # NET_VENDOR_3SNIC

drivers/net/ethernet/3snic/Makefile

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the 3SNIC network device drivers.
+#
+
+obj-$(CONFIG_SSSNIC) += sssnic/

drivers/net/ethernet/3snic/sssnic/Kconfig

@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# 3SNIC network device configuration
+#
+
+config SSSNIC
+	tristate "3SNIC Ethernet Controller SSSNIC Support"
+	depends on PCI
+	depends on ARM64 || X86_64
+	default y
+	help
+	  This driver supports 3SNIC Ethernet Controller SSSNIC device.
+	  For more information about this product, go to the product
+	  description with smart NIC:
+
+	  <http://www.3snic.com>
+
+	  To compile this driver as a module, choose M here. The module
+	  will be called sssnic.

drivers/net/ethernet/3snic/sssnic/Makefile

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the 3SNIC network device drivers.
+#
+
+obj-$(CONFIG_SSSNIC) += nic/

drivers/net/ethernet/3snic/sssnic/hw/include/sss_adapter.h

@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2021 3snic Technologies Co., Ltd */
+
+#ifndef SSS_ADAPTER_H
+#define SSS_ADAPTER_H
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/list.h>
+#include <linux/atomic.h>
+#include <linux/spinlock.h>
+
+#include "sss_hw_common.h"
+#include "sss_hw_uld_driver.h"
+#include "sss_hw_svc_cap.h"
+#include "sss_sriov_info.h"
+
+#define SSS_MAX_FUNC 4096
+
+struct sss_card_node {
+	struct list_head node;
+	struct list_head func_list;
+	char chip_name[IFNAMSIZ];
+	u8 bus_id;
+	u8 resvd[7];
+	u16 func_num;
+	atomic_t channel_timeout_cnt;
+	void *func_handle_array[SSS_MAX_FUNC];
+	void *dbgtool_info;
+};
+
+/* Structure pcidev private */
+struct sss_pci_adapter {
+	struct pci_dev *pcidev;
+	void *hwdev;
+
+	struct sss_hal_dev hal_dev;
+
+	/* Record the upper driver object address,
+	 * such as nic_dev and toe_dev, fc_dev
+	 */
+	void *uld_dev[SSS_SERVICE_TYPE_MAX];
+
+	/* Record the upper driver object name */
+	char uld_dev_name[SSS_SERVICE_TYPE_MAX][IFNAMSIZ];
+
+	/* Manage all function device linked by list */
+	struct list_head node;
+
+	void __iomem *cfg_reg_bar;
+	void __iomem *intr_reg_bar;
+	void __iomem *mgmt_reg_bar;
+	void __iomem *db_reg_bar;
+	u64 db_dwqe_len;
+	u64 db_base_paddr;
+
+	struct sss_card_node *chip_node;
+
+	int init_state;
+
+	struct sss_sriov_info sriov_info;
+
+	atomic_t ref_cnt;
+
+	atomic_t uld_ref_cnt[SSS_SERVICE_TYPE_MAX];
+	spinlock_t uld_lock; /* protect uld probe and remove */
+
+	/* set when uld driver processing event */
+	unsigned long uld_run_state;
+
+	unsigned long uld_attach_state;
+
+	/* lock for attach/detach uld */
+	struct mutex uld_attach_mutex;
+
+	spinlock_t dettach_uld_lock; /* spin lock for uld_attach_state access */
+};
+#endif

drivers/net/ethernet/3snic/sssnic/hw/include/sss_adm_info.h

@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2021 3snic Technologies Co., Ltd */
+
+#ifndef SSS_ADM_INFO_H
+#define SSS_ADM_INFO_H
+
+#include <linux/types.h>
+#include <linux/semaphore.h>
+#include <linux/spinlock.h>
+#include <linux/completion.h>
+
+#include "sss_hw_common.h"
+
+enum sss_adm_msg_type {
+	/* write to mgmt cpu command with completion  */
+	SSS_ADM_MSG_WRITE_TO_MGMT_MODULE		= 2,
+
+	/* multi read command with completion notification */
+	SSS_ADM_MSG_MULTI_READ				= 3,
+
+	/* write command without completion notification */
+	SSS_ADM_MSG_POLL_WRITE				= 4,
+
+	/* read command without completion notification */
+	SSS_ADM_MSG_POLL_READ				= 5,
+
+	/* read from mgmt cpu command with completion */
+	SSS_ADM_MSG_WRITE_ASYNC_TO_MGMT_MODULE	= 6,
+
+	SSS_ADM_MSG_MAX,
+};
+
+struct sss_adm_msg_state {
+	u64 head;
+	u32 desc_buf;
+	u32 elem_hi;
+	u32 elem_lo;
+	u32 rsvd0;
+	u64 rsvd1;
+};
+
+/* HW struct */
+struct sss_adm_msg_elem {
+	u64 control;
+
+	u64 next_elem_paddr;
+
+	u64 desc;
+
+	/* HW struct */
+	union {
+		struct {
+			u64 hw_msg_paddr;
+		} write;
+
+		struct {
+			u64 hw_wb_reply_paddr;
+			u64 hw_msg_paddr;
+		} read;
+	};
+};
+
+struct sss_adm_msg_reply_fmt {
+	u64		head;
+	u64		reply;
+};
+
+struct sss_adm_msg_elem_ctx {
+	struct sss_adm_msg_elem	*elem_vaddr;
+
+	void				*adm_msg_vaddr;
+
+	struct sss_adm_msg_reply_fmt	*reply_fmt;
+
+	struct completion	done;
+	int					state;
+
+	u32		 store_pi;
+	void	*hwdev;
+};
+
+struct sss_adm_msg {
+	void	*hwdev;
+
+	enum sss_adm_msg_type		msg_type;
+
+	u32				elem_num;
+
+	u16				elem_size;
+	u16				reply_size;
+
+	u32				pi;
+	u32				ci;
+
+	struct semaphore				sem;
+	spinlock_t			async_lock; /* protect adm msg async and sync */
+	dma_addr_t						wb_state_paddr;
+
+	dma_addr_t						head_elem_paddr;
+
+	struct sss_adm_msg_state		*wb_state;
+
+	struct sss_adm_msg_elem		*head_node;
+
+	struct sss_adm_msg_elem_ctx	*elem_ctx;
+	struct sss_adm_msg_elem		*now_node;
+
+	struct sss_dma_addr_align		elem_addr;
+
+	u8				*elem_vaddr_base;
+	u8				*reply_vaddr_base;
+	u8				*buf_vaddr_base;
+
+	u64				elem_paddr_base;
+	u64				reply_paddr_base;
+	u64				buf_paddr_base;
+	u64				elem_size_align;
+	u64				reply_size_align;
+	u64				buf_size_align;
+};
+#endif

drivers/net/ethernet/3snic/sssnic/hw/include/sss_aeq_info.h

@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright(c) 2021 3snic Technologies Co., Ltd */
+
+#ifndef SSS_AEQ_INFO_H
+#define SSS_AEQ_INFO_H
+
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+#include "sss_eq_info.h"
+#include "sss_hw_aeq.h"
+
+#define SSS_MAX_AEQ				4
+
+typedef void (*sss_aeq_hw_event_handler_t)(void *pri_handle, u8 *data, u8 size);
+typedef u8 (*sss_aeq_sw_event_handler_t)(void *pri_handle, u8 event, u8 *data);
+
+struct sss_aeq_info {
+	void						*hwdev;
+
+	sss_aeq_hw_event_handler_t			hw_event_handler[SSS_AEQ_EVENT_MAX];
+	void						*hw_event_data[SSS_AEQ_EVENT_MAX];
+	sss_aeq_sw_event_handler_t			sw_event_handler[SSS_AEQ_SW_EVENT_MAX];
+	void						*sw_event_data[SSS_AEQ_SW_EVENT_MAX];
+	unsigned long				hw_event_handler_state[SSS_AEQ_EVENT_MAX];
+	unsigned long				sw_event_handler_state[SSS_AEQ_SW_EVENT_MAX];
+
+	struct sss_eq				aeq[SSS_MAX_AEQ];
+	u16							num;
+	u16							rsvd1;
+	u32							rsvd2;
+	struct workqueue_struct		*workq;
+};
+#endif