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Jzjerry/readme.md

Hi, I'm JIANG (Jerry) Zijun

Click here to learn more about me!

✨Fancy Stuffs✨

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Code Time

Profile Views

I'm an Early 🐤

🌞 Morning                60 commits          █░░░░░░░░░░░░░░░░░░░░░░░░   04.57 % 
🌆 Daytime                695 commits         █████████████░░░░░░░░░░░░   52.89 % 
🌃 Evening                481 commits         █████████░░░░░░░░░░░░░░░░   36.61 % 
🌙 Night                  78 commits          █░░░░░░░░░░░░░░░░░░░░░░░░   05.94 % 

📅 I'm Most Productive on Monday

Monday                   270 commits         █████░░░░░░░░░░░░░░░░░░░░   20.55 % 
Tuesday                  254 commits         █████░░░░░░░░░░░░░░░░░░░░   19.33 % 
Wednesday                194 commits         ████░░░░░░░░░░░░░░░░░░░░░   14.76 % 
Thursday                 211 commits         ████░░░░░░░░░░░░░░░░░░░░░   16.06 % 
Friday                   200 commits         ████░░░░░░░░░░░░░░░░░░░░░   15.22 % 
Saturday                 92 commits          ██░░░░░░░░░░░░░░░░░░░░░░░   07.00 % 
Sunday                   93 commits          ██░░░░░░░░░░░░░░░░░░░░░░░   07.08 % 

📊 This Week I Spent My Time On

🕑︎ Time Zone: Asia/Shanghai

💬 Programming Languages: 
C                        15 hrs 55 mins      ███████████████░░░░░░░░░░   61.76 % 
Python                   6 hrs 6 mins        ██████░░░░░░░░░░░░░░░░░░░   23.68 % 
Log File                 58 mins             █░░░░░░░░░░░░░░░░░░░░░░░░   03.80 % 
Scala                    56 mins             █░░░░░░░░░░░░░░░░░░░░░░░░   03.64 % 
Makefile                 32 mins             █░░░░░░░░░░░░░░░░░░░░░░░░   02.12 % 

🔥 Editors: 
VS Code                  25 hrs 47 mins      █████████████████████████   100.00 % 

💻 Operating System: 
WSL                      25 hrs 2 mins       ████████████████████████░   97.07 % 
Linux                    45 mins             █░░░░░░░░░░░░░░░░░░░░░░░░   02.93 % 

I Mostly Code in Python

Python                   11 repos            ███████░░░░░░░░░░░░░░░░░░   26.19 % 
Scala                    7 repos             ████░░░░░░░░░░░░░░░░░░░░░   16.67 % 
C                        7 repos             ████░░░░░░░░░░░░░░░░░░░░░   16.67 % 
Verilog                  6 repos             ████░░░░░░░░░░░░░░░░░░░░░   14.29 % 
C++                      6 repos             ████░░░░░░░░░░░░░░░░░░░░░   14.29 % 

Last Updated on 04/09/2024 18:39:15 UTC

Pinned Loading

  1. Jzjerry.github.io Jzjerry.github.io Public

    HTML 2

  2. VexRiscv VexRiscv Public

    Forked from SpinalHDL/VexRiscv

    A FPGA friendly 32 bit RISC-V CPU implementation

    Assembly

  3. VexiiRiscv VexiiRiscv Public

    Forked from SpinalHDL/VexiiRiscv

    Scala

  4. NodeMCU_LCD NodeMCU_LCD Public

    A simple monitor for Bilibili livers based on ESP8266 & TFT_eSPI

    C++ 2