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drm/v3d: fix up register addresses for V3D 7.x
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This patch updates a number of register addresses that have
been changed in Raspberry Pi 5 (V3D 7.1) and updates the
code to use the corresponding registers and addresses based
on the actual V3D version.

Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Maíra Canal <mcanal@igalia.com>
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231031073859.25298-3-itoral@igalia.com
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@itoral @mairacanal
itoral authored and mairacanal committed Nov 2, 2023
1 parent 1118d10 commit 0ad5bc1
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Showing 5 changed files with 204 additions and 156 deletions.
178 changes: 101 additions & 77 deletions drivers/gpu/drm/v3d/v3d_debugfs.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,69 +12,83 @@
#include "v3d_drv.h"
#include "v3d_regs.h"

#define REGDEF(reg) { reg, #reg }
#define REGDEF(min_ver, max_ver, reg) { min_ver, max_ver, reg, #reg }
struct v3d_reg_def {
u32 min_ver;
u32 max_ver;
u32 reg;
const char *name;
};

static const struct v3d_reg_def v3d_hub_reg_defs[] = {
REGDEF(V3D_HUB_AXICFG),
REGDEF(V3D_HUB_UIFCFG),
REGDEF(V3D_HUB_IDENT0),
REGDEF(V3D_HUB_IDENT1),
REGDEF(V3D_HUB_IDENT2),
REGDEF(V3D_HUB_IDENT3),
REGDEF(V3D_HUB_INT_STS),
REGDEF(V3D_HUB_INT_MSK_STS),

REGDEF(V3D_MMU_CTL),
REGDEF(V3D_MMU_VIO_ADDR),
REGDEF(V3D_MMU_VIO_ID),
REGDEF(V3D_MMU_DEBUG_INFO),
REGDEF(33, 42, V3D_HUB_AXICFG),
REGDEF(33, 71, V3D_HUB_UIFCFG),
REGDEF(33, 71, V3D_HUB_IDENT0),
REGDEF(33, 71, V3D_HUB_IDENT1),
REGDEF(33, 71, V3D_HUB_IDENT2),
REGDEF(33, 71, V3D_HUB_IDENT3),
REGDEF(33, 71, V3D_HUB_INT_STS),
REGDEF(33, 71, V3D_HUB_INT_MSK_STS),

REGDEF(33, 71, V3D_MMU_CTL),
REGDEF(33, 71, V3D_MMU_VIO_ADDR),
REGDEF(33, 71, V3D_MMU_VIO_ID),
REGDEF(33, 71, V3D_MMU_DEBUG_INFO),

REGDEF(71, 71, V3D_GMP_STATUS(71)),
REGDEF(71, 71, V3D_GMP_CFG(71)),
REGDEF(71, 71, V3D_GMP_VIO_ADDR(71)),
};

static const struct v3d_reg_def v3d_gca_reg_defs[] = {
REGDEF(V3D_GCA_SAFE_SHUTDOWN),
REGDEF(V3D_GCA_SAFE_SHUTDOWN_ACK),
REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN),
REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN_ACK),
};

static const struct v3d_reg_def v3d_core_reg_defs[] = {
REGDEF(V3D_CTL_IDENT0),
REGDEF(V3D_CTL_IDENT1),
REGDEF(V3D_CTL_IDENT2),
REGDEF(V3D_CTL_MISCCFG),
REGDEF(V3D_CTL_INT_STS),
REGDEF(V3D_CTL_INT_MSK_STS),
REGDEF(V3D_CLE_CT0CS),
REGDEF(V3D_CLE_CT0CA),
REGDEF(V3D_CLE_CT0EA),
REGDEF(V3D_CLE_CT1CS),
REGDEF(V3D_CLE_CT1CA),
REGDEF(V3D_CLE_CT1EA),

REGDEF(V3D_PTB_BPCA),
REGDEF(V3D_PTB_BPCS),

REGDEF(V3D_GMP_STATUS),
REGDEF(V3D_GMP_CFG),
REGDEF(V3D_GMP_VIO_ADDR),

REGDEF(V3D_ERR_FDBGO),
REGDEF(V3D_ERR_FDBGB),
REGDEF(V3D_ERR_FDBGS),
REGDEF(V3D_ERR_STAT),
REGDEF(33, 71, V3D_CTL_IDENT0),
REGDEF(33, 71, V3D_CTL_IDENT1),
REGDEF(33, 71, V3D_CTL_IDENT2),
REGDEF(33, 71, V3D_CTL_MISCCFG),
REGDEF(33, 71, V3D_CTL_INT_STS),
REGDEF(33, 71, V3D_CTL_INT_MSK_STS),
REGDEF(33, 71, V3D_CLE_CT0CS),
REGDEF(33, 71, V3D_CLE_CT0CA),
REGDEF(33, 71, V3D_CLE_CT0EA),
REGDEF(33, 71, V3D_CLE_CT1CS),
REGDEF(33, 71, V3D_CLE_CT1CA),
REGDEF(33, 71, V3D_CLE_CT1EA),

REGDEF(33, 71, V3D_PTB_BPCA),
REGDEF(33, 71, V3D_PTB_BPCS),

REGDEF(33, 41, V3D_GMP_STATUS(33)),
REGDEF(33, 41, V3D_GMP_CFG(33)),
REGDEF(33, 41, V3D_GMP_VIO_ADDR(33)),

REGDEF(33, 71, V3D_ERR_FDBGO),
REGDEF(33, 71, V3D_ERR_FDBGB),
REGDEF(33, 71, V3D_ERR_FDBGS),
REGDEF(33, 71, V3D_ERR_STAT),
};

static const struct v3d_reg_def v3d_csd_reg_defs[] = {
REGDEF(V3D_CSD_STATUS),
REGDEF(V3D_CSD_CURRENT_CFG0),
REGDEF(V3D_CSD_CURRENT_CFG1),
REGDEF(V3D_CSD_CURRENT_CFG2),
REGDEF(V3D_CSD_CURRENT_CFG3),
REGDEF(V3D_CSD_CURRENT_CFG4),
REGDEF(V3D_CSD_CURRENT_CFG5),
REGDEF(V3D_CSD_CURRENT_CFG6),
REGDEF(41, 71, V3D_CSD_STATUS),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG0(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG1(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG2(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG3(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG4(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG5(41)),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG6(41)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG0(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG1(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG2(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG3(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG4(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG5(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG6(71)),
REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG7),
};

static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
Expand All @@ -85,38 +99,41 @@ static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
int i, core;

for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) {
seq_printf(m, "%s (0x%04x): 0x%08x\n",
v3d_hub_reg_defs[i].name, v3d_hub_reg_defs[i].reg,
V3D_READ(v3d_hub_reg_defs[i].reg));
const struct v3d_reg_def *def = &v3d_hub_reg_defs[i];

if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) {
seq_printf(m, "%s (0x%04x): 0x%08x\n",
def->name, def->reg, V3D_READ(def->reg));
}
}

if (v3d->ver < 41) {
for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
const struct v3d_reg_def *def = &v3d_gca_reg_defs[i];

if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) {
seq_printf(m, "%s (0x%04x): 0x%08x\n",
v3d_gca_reg_defs[i].name,
v3d_gca_reg_defs[i].reg,
V3D_GCA_READ(v3d_gca_reg_defs[i].reg));
def->name, def->reg, V3D_GCA_READ(def->reg));
}
}

for (core = 0; core < v3d->cores; core++) {
for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) {
seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
core,
v3d_core_reg_defs[i].name,
v3d_core_reg_defs[i].reg,
V3D_CORE_READ(core,
v3d_core_reg_defs[i].reg));
const struct v3d_reg_def *def = &v3d_core_reg_defs[i];

if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) {
seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
core, def->name, def->reg,
V3D_CORE_READ(core, def->reg));
}
}

if (v3d_has_csd(v3d)) {
for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) {
for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) {
const struct v3d_reg_def *def = &v3d_csd_reg_defs[i];

if (v3d->ver >= def->min_ver && v3d->ver <= def->max_ver) {
seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
core,
v3d_csd_reg_defs[i].name,
v3d_csd_reg_defs[i].reg,
V3D_CORE_READ(core,
v3d_csd_reg_defs[i].reg));
core, def->name, def->reg,
V3D_CORE_READ(core, def->reg));
}
}
}
Expand Down Expand Up @@ -147,8 +164,10 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU));
seq_printf(m, "TFU: %s\n",
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU));
seq_printf(m, "TSY: %s\n",
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
if (v3d->ver <= 42) {
seq_printf(m, "TSY: %s\n",
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
}
seq_printf(m, "MSO: %s\n",
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_MSO));
seq_printf(m, "L3C: %s (%dkb)\n",
Expand Down Expand Up @@ -177,10 +196,14 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
seq_printf(m, " QPUs: %d\n", nslc * qups);
seq_printf(m, " Semaphores: %d\n",
V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
seq_printf(m, " BCG int: %d\n",
(ident2 & V3D_IDENT2_BCG_INT) != 0);
seq_printf(m, " Override TMU: %d\n",
(misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
if (v3d->ver <= 42) {
seq_printf(m, " BCG int: %d\n",
(ident2 & V3D_IDENT2_BCG_INT) != 0);
}
if (v3d->ver < 40) {
seq_printf(m, " Override TMU: %d\n",
(misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
}
}

return 0;
Expand Down Expand Up @@ -212,14 +235,15 @@ static int v3d_measure_clock(struct seq_file *m, void *unused)
int measure_ms = 1000;

if (v3d->ver >= 40) {
int cycle_count_reg = V3D_PCTR_CYCLE_COUNT(v3d->ver);
V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT,
V3D_SET_FIELD(cycle_count_reg,
V3D_PCTR_S0));
V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
} else {
V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
V3D_PCTR_CYCLE_COUNT);
V3D_PCTR_CYCLE_COUNT(v3d->ver));
V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
V3D_V3_PCTR_0_EN_ENABLE |
Expand Down
4 changes: 2 additions & 2 deletions drivers/gpu/drm/v3d/v3d_gem.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -47,9 +47,9 @@ v3d_init_hw_state(struct v3d_dev *v3d)
static void
v3d_idle_axi(struct v3d_dev *v3d, int core)
{
V3D_CORE_WRITE(core, V3D_GMP_CFG, V3D_GMP_CFG_STOP_REQ);
V3D_CORE_WRITE(core, V3D_GMP_CFG(v3d->ver), V3D_GMP_CFG_STOP_REQ);

if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS) &
if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS(v3d->ver)) &
(V3D_GMP_STATUS_RD_COUNT_MASK |
V3D_GMP_STATUS_WR_COUNT_MASK |
V3D_GMP_STATUS_CFG_BUSY)) == 0, 100)) {
Expand Down
46 changes: 26 additions & 20 deletions drivers/gpu/drm/v3d/v3d_irq.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,16 +19,17 @@
#include "v3d_regs.h"
#include "v3d_trace.h"

#define V3D_CORE_IRQS ((u32)(V3D_INT_OUTOMEM | \
V3D_INT_FLDONE | \
V3D_INT_FRDONE | \
V3D_INT_CSDDONE | \
V3D_INT_GMPV))

#define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV | \
V3D_HUB_INT_MMU_PTI | \
V3D_HUB_INT_MMU_CAP | \
V3D_HUB_INT_TFUC))
#define V3D_CORE_IRQS(ver) ((u32)(V3D_INT_OUTOMEM | \
V3D_INT_FLDONE | \
V3D_INT_FRDONE | \
V3D_INT_CSDDONE(ver) | \
(ver < 71 ? V3D_INT_GMPV : 0)))

#define V3D_HUB_IRQS(ver) ((u32)(V3D_HUB_INT_MMU_WRV | \
V3D_HUB_INT_MMU_PTI | \
V3D_HUB_INT_MMU_CAP | \
V3D_HUB_INT_TFUC | \
(ver >= 71 ? V3D_V7_HUB_INT_GMPV : 0)))

static irqreturn_t
v3d_hub_irq(int irq, void *arg);
Expand Down Expand Up @@ -115,7 +116,7 @@ v3d_irq(int irq, void *arg)
status = IRQ_HANDLED;
}

if (intsts & V3D_INT_CSDDONE) {
if (intsts & V3D_INT_CSDDONE(v3d->ver)) {
struct v3d_fence *fence =
to_v3d_fence(v3d->csd_job->base.irq_fence);

Expand All @@ -127,7 +128,7 @@ v3d_irq(int irq, void *arg)
/* We shouldn't be triggering these if we have GMP in
* always-allowed mode.
*/
if (intsts & V3D_INT_GMPV)
if (v3d->ver < 71 && (intsts & V3D_INT_GMPV))
dev_err(v3d->drm.dev, "GMP violation\n");

/* V3D 4.2 wires the hub and core IRQs together, so if we &
Expand Down Expand Up @@ -197,6 +198,11 @@ v3d_hub_irq(int irq, void *arg)
status = IRQ_HANDLED;
}

if (v3d->ver >= 71 && (intsts & V3D_V7_HUB_INT_GMPV)) {
dev_err(v3d->drm.dev, "GMP Violation\n");
status = IRQ_HANDLED;
}

return status;
}

Expand All @@ -211,8 +217,8 @@ v3d_irq_init(struct v3d_dev *v3d)
* for us.
*/
for (core = 0; core < v3d->cores; core++)
V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver));
V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver));

irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1);
if (irq1 == -EPROBE_DEFER)
Expand Down Expand Up @@ -256,12 +262,12 @@ v3d_irq_enable(struct v3d_dev *v3d)

/* Enable our set of interrupts, masking out any others. */
for (core = 0; core < v3d->cores; core++) {
V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS);
V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS);
V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS(v3d->ver));
V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS(v3d->ver));
}

V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS);
V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS);
V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS(v3d->ver));
V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS(v3d->ver));
}

void
Expand All @@ -276,8 +282,8 @@ v3d_irq_disable(struct v3d_dev *v3d)

/* Clear any pending interrupts we might have left. */
for (core = 0; core < v3d->cores; core++)
V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver));
V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver));

cancel_work_sync(&v3d->overflow_mem_work);
}
Expand Down
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