cva6: Remove global imports (openhwgroup#489)

* remove global import and fix same name: is_branch
* remove the commented import statements and rename `is_branch` to `op_is_branch`

Signed-off-by: Ruige Lee <295054118@qq.com>

include/ariane_pkg.sv

@@ -481,7 +481,7 @@ package ariane_pkg;
         logic [TRANS_ID_BITS-1:0] trans_id;
     } fu_data_t;
 
-    function automatic logic is_branch (input fu_op op);
+    function automatic logic op_is_branch (input fu_op op);
         unique case (op) inside
             EQ, NE, LTS, GES, LTU, GEU: return 1'b1;
             default                   : return 1'b0; // all other ops

include/axi_intf.sv

@@ -13,7 +13,6 @@
 //
 // This file defines the interfaces we support.
 
-import axi_pkg::*;
 
 
 /// An AXI4 interface.
@@ -24,6 +23,8 @@ interface AXI_BUS #(
   parameter AXI_USER_WIDTH = -1
 );
 
+  import axi_pkg::*;
+
   localparam AXI_STRB_WIDTH = AXI_DATA_WIDTH / 8;
 
   typedef logic [AXI_ID_WIDTH-1:0]   id_t;

src/alu.sv

@@ -17,9 +17,8 @@
 // Date: 19.03.2017
 // Description: Ariane ALU based on RI5CY's ALU
 
-import ariane_pkg::*;
 
-module alu (
+module alu import ariane_pkg::*;(
     input  logic                     clk_i,          // Clock
     input  logic                     rst_ni,         // Asynchronous reset active low
     input  fu_data_t                 fu_data_i,

src/ariane.sv

@@ -22,9 +22,8 @@ import "DPI-C" function void dromajo_step(int     hart_id,
 import "DPI-C" function void init_dromajo(string cfg_f_name);
 `endif
 
-import ariane_pkg::*;
 
-module ariane #(
+module ariane import ariane_pkg::*; #(
   parameter ariane_pkg::ariane_cfg_t ArianeCfg     = ariane_pkg::ArianeDefaultConfig
 ) (
   input  logic                         clk_i,

src/axi_shim.sv

@@ -18,7 +18,6 @@
  * 
  */
 
-import std_cache_pkg::*;
 
 module axi_shim #(
     parameter int unsigned AxiNumWords       = 4, // data width in dwords, this is also the maximum burst length, must be >=2

src/branch_unit.sv

@@ -65,7 +65,7 @@ module branch_unit (
             resolved_branch_o.target_address = (branch_comp_res_i) ? target_address : next_pc;
             resolved_branch_o.is_taken = branch_comp_res_i;
             // check the outcome of the branch speculation
-            if (ariane_pkg::is_branch(fu_data_i.operator) && branch_comp_res_i != (branch_predict_i.cf == ariane_pkg::Branch)) begin
+            if (ariane_pkg::op_is_branch(fu_data_i.operator) && branch_comp_res_i != (branch_predict_i.cf == ariane_pkg::Branch)) begin
                 // we mis-predicted the outcome
                 // if the outcome doesn't match we've got a mis-predict
                 resolved_branch_o.is_mispredict  = 1'b1;

src/cache_subsystem/cache_ctrl.sv

@@ -17,10 +17,8 @@
 //
 // Description: Cache controller
 
-import ariane_pkg::*;
-import std_cache_pkg::*;
 
-module cache_ctrl #(
+module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
     parameter logic [63:0] CACHE_START_ADDR  = 64'h4000_0000
 ) (
     input  logic                                 clk_i,     // Clock

src/cache_subsystem/std_cache_subsystem.sv

@@ -14,10 +14,8 @@
 // Description: Standard Ariane cache subsystem with instruction cache and
 //              write-back data cache.
 
-import ariane_pkg::*;
-import std_cache_pkg::*;
 
-module std_cache_subsystem #(
+module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
   parameter logic [63:0] CACHE_START_ADDR = 64'h4000_0000
 ) (
     input logic                            clk_i,

src/cache_subsystem/std_icache.sv

@@ -13,10 +13,8 @@
 // ------------------------------
 // Instruction Cache
 // ------------------------------
-import ariane_pkg::*;
-import std_cache_pkg::*;
 
-module std_icache (
+module std_icache import ariane_pkg::*; import std_cache_pkg::*; (
     input  logic                     clk_i,
     input  logic                     rst_ni,
     input riscv::priv_lvl_t          priv_lvl_i,

src/cache_subsystem/std_nbdcache.sv

@@ -12,9 +12,8 @@
 // Date: 13.10.2017
 // Description: Nonblocking private L1 dcache
 
-import ariane_pkg::*;
 
-module std_nbdcache import std_cache_pkg::*; #(
+module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #(
     parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000
 )(
     input  logic                           clk_i,       // Clock

src/cache_subsystem/wt_axi_adapter.sv

@@ -13,10 +13,8 @@
 // Description: adapter module to connect the L1D$ and L1I$ to a 64bit AXI bus.
 //
 
-import ariane_pkg::*;
-import wt_cache_pkg::*;
 
-module wt_axi_adapter #(
+module wt_axi_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
   parameter int unsigned ReqFifoDepth  = 2,
   parameter int unsigned MetaFifoDepth = wt_cache_pkg::DCACHE_MAX_TX
 ) (

src/cache_subsystem/wt_cache_subsystem.sv

@@ -18,10 +18,8 @@
 //              with a standard 64 bit AXI interface instead of the OpenPiton
 //              L1.5 interface.
 
-import ariane_pkg::*;
-import wt_cache_pkg::*;
 
-module wt_cache_subsystem #(
+module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
   parameter ariane_pkg::ariane_cfg_t ArianeCfg       = ariane_pkg::ArianeDefaultConfig  // contains cacheable regions
 ) (
   input logic                            clk_i,

src/cache_subsystem/wt_dcache.sv

@@ -12,10 +12,8 @@
 // Date: 13.09.2018
 // Description: Instruction cache that is compatible with openpiton.
 
-import ariane_pkg::*;
-import wt_cache_pkg::*;
 
-module wt_dcache #(
+module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(
   // ID to be used for read and AMO transactions.
   // note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions
   parameter logic [CACHE_ID_WIDTH-1:0]   RdAmoTxId          = 1,

src/cache_subsystem/wt_dcache_ctrl.sv

@@ -12,10 +12,8 @@
 // Date: 13.09.2018
 // Description: DCache controller for read port
 
-import ariane_pkg::*;
-import wt_cache_pkg::*;
 
-module wt_dcache_ctrl #(
+module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
   parameter logic [CACHE_ID_WIDTH-1:0]  RdTxId    = 1,                              // ID to use for read transactions
   parameter ariane_pkg::ariane_cfg_t    ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions
 ) (

src/cache_subsystem/wt_dcache_mem.sv

@@ -25,10 +25,8 @@
 //        4) Read ports with same priority are RR arbited. but high prio ports (rd_prio_i[port_nr] = '1b1) will stall
 //           low prio ports (rd_prio_i[port_nr] = '1b0)
 
-import ariane_pkg::*;
-import wt_cache_pkg::*;
 
-module wt_dcache_mem #(
+module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #(
   parameter bit          Axi64BitCompliant  = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter
   parameter int unsigned NumPorts           = 3
 ) (

src/cache_subsystem/wt_dcache_missunit.sv

@@ -13,10 +13,8 @@
 // Description: miss controller for wb dcache. Note that the current assumption
 // is that the port with the highest index issues writes instead of reads.
 
-import ariane_pkg::*;
-import wt_cache_pkg::*;
 
-module wt_dcache_missunit #(
+module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #(
   parameter bit                         Axi64BitCompliant  = 1'b0, // set this to 1 when using in conjunction with 64bit AXI bus adapter
   parameter logic [CACHE_ID_WIDTH-1:0]  AmoTxId            = 1,    // TX id to be used for AMOs
   parameter int unsigned                NumPorts           = 3     // number of miss ports

src/cache_subsystem/wt_dcache_wbuffer.sv

@@ -48,10 +48,8 @@
 //    then, only the NC word is written into the write buffer and no further write requests are acknowledged until that
 //    word has been evicted from the write buffer.
 
-import ariane_pkg::*;
-import wt_cache_pkg::*;
 
-module wt_dcache_wbuffer #(
+module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #(
   parameter ariane_pkg::ariane_cfg_t    ArianeCfg          = ariane_pkg::ArianeDefaultConfig     // contains cacheable regions
 ) (
   input  logic                               clk_i,          // Clock

src/cache_subsystem/wt_icache.sv

@@ -24,10 +24,8 @@
 // 3) NC accesses to I/O space are expected to return 32bit from memory.
 //
 
-import ariane_pkg::*;
-import wt_cache_pkg::*;
 
-module wt_icache  #(
+module wt_icache import ariane_pkg::*; import wt_cache_pkg::*; #(
   parameter logic [CACHE_ID_WIDTH-1:0]  RdTxId             = 0,                                  // ID to be used for read transactions
   parameter ariane_pkg::ariane_cfg_t    ArianeCfg          = ariane_pkg::ArianeDefaultConfig     // contains cacheable regions
 ) (

src/cache_subsystem/wt_l15_adapter.sv

@@ -48,10 +48,8 @@
 //           https://parallel.princeton.edu/openpiton/docs/micro_arch.pdf
 //
 
-import ariane_pkg::*;
-import wt_cache_pkg::*;
 
-module wt_l15_adapter #(
+module wt_l15_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
   parameter bit          SwapEndianess = 1
 ) (
   input logic                  clk_i,

src/commit_stage.sv

@@ -12,9 +12,8 @@
 // Date: 15.04.2017
 // Description: Commits to the architectural state resulting from the scoreboard.
 
-import ariane_pkg::*;
 
-module commit_stage #(
+module commit_stage import ariane_pkg::*; #(
     parameter int unsigned NR_COMMIT_PORTS = 2
 )(
     input  logic                                    clk_i,

src/compressed_decoder.sv

@@ -18,7 +18,6 @@
 // Description:    Decodes RISC-V compressed instructions into their RV32
 //                 equivalent. This module is fully combinatorial.
 
-import ariane_pkg::*;
 
 module compressed_decoder
 (

src/controller.sv

@@ -12,9 +12,8 @@
 // Date: 08.05.2017
 // Description: Flush controller
 
-import ariane_pkg::*;
 
-module controller (
+module controller import ariane_pkg::*; (
     input  logic            clk_i,
     input  logic            rst_ni,
     output logic            set_pc_commit_o,        // Set PC om PC Gen

src/csr_buffer.sv

@@ -13,9 +13,8 @@
 // Description: Buffer to hold CSR address, this acts like a functional unit
 //              to the scoreboard.
 
-import ariane_pkg::*;
 
-module csr_buffer (
+module csr_buffer import ariane_pkg::*; (
     input  logic                     clk_i,          // Clock
     input  logic                     rst_ni,         // Asynchronous reset active low
     input  logic                     flush_i,

src/csr_regfile.sv

@@ -12,9 +12,8 @@
 // Date: 05.05.2017
 // Description: CSR Register File as specified by RISC-V
 
-import ariane_pkg::*;
 
-module csr_regfile #(
+module csr_regfile import ariane_pkg::*; #(
     parameter logic [63:0] DmBaseAddress   = 64'h0, // debug module base address
     parameter int          AsidWidth       = 1,
     parameter int unsigned NrCommitPorts   = 2,

src/decoder.sv

@@ -18,9 +18,8 @@
 // Description: Issues instruction from the scoreboard and fetches the operands
 //              This also includes all the forwarding logic
 //
-import ariane_pkg::*;
 
-module decoder (
+module decoder import ariane_pkg::*; (
     input  logic               debug_req_i,             // external debug request
     input  logic [riscv::VLEN-1:0] pc_i,                // PC from IF
     input  logic               is_compressed_i,         // is a compressed instruction

src/ex_stage.sv

@@ -13,9 +13,8 @@
 // Date: 19.04.2017
 // Description: Instantiation of all functional units residing in the execute stage
 
-import ariane_pkg::*;
 
-module ex_stage #(
+module ex_stage import ariane_pkg::*; #(
     parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
 ) (
     input  logic                                   clk_i,    // Clock

src/fpu_wrap.sv

@@ -12,9 +12,8 @@
 // Date: 12.04.2018
 // Description: Wrapper for the floating-point unit
 
-import ariane_pkg::*;
 
-module fpu_wrap (
+module fpu_wrap import ariane_pkg::*; (
   input  logic                     clk_i,
   input  logic                     rst_ni,
   input  logic                     flush_i,

src/frontend/frontend.sv

@@ -14,9 +14,8 @@
 //
 // This module interfaces with the instruction cache, handles control
 // change request from the back-end and does branch prediction.
-import ariane_pkg::*;
 
-module frontend #(
+module frontend import ariane_pkg::*; #(
   parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
 ) (
   input  logic               clk_i,              // Clock

src/instr_realign.sv

@@ -19,9 +19,8 @@
 // Furthermore we need to handle the case if we want to start fetching from an unaligned
 // instruction e.g. a branch.
 
-import ariane_pkg::*;
 
-module instr_realign (
+module instr_realign import ariane_pkg::*; (
     input  logic                              clk_i,
     input  logic                              rst_ni,
     input  logic                              flush_i,

src/issue_read_operands.sv

@@ -13,9 +13,8 @@
 // Description: Issues instruction from the scoreboard and fetches the operands
 //              This also includes all the forwarding logic
 
-import ariane_pkg::*;
 
-module issue_read_operands #(
+module issue_read_operands import ariane_pkg::*; #(
     parameter int unsigned NR_COMMIT_PORTS = 2
 )(
     input  logic                                   clk_i,    // Clock

src/issue_stage.sv

@@ -13,9 +13,8 @@
 // Description: Issue stage dispatches instructions to the FUs and keeps track of them
 //              in a scoreboard like data-structure.
 
-import ariane_pkg::*;
 
-module issue_stage #(
+module issue_stage import ariane_pkg::*; #(
     parameter int unsigned NR_ENTRIES = 8,
     parameter int unsigned NR_WB_PORTS = 4,
     parameter int unsigned NR_COMMIT_PORTS = 2

src/load_store_unit.sv

@@ -12,9 +12,8 @@
 // Date: 19.04.2017
 // Description: Load Store Unit, handles address calculation and memory interface signals
 
-import ariane_pkg::*;
 
-module load_store_unit #(
+module load_store_unit import ariane_pkg::*; #(
     parameter int unsigned ASID_WIDTH = 1,
     parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
 )(
@@ -400,7 +399,7 @@ endmodule
 // the LSU control should sample it and store it for later application to the units. It does so, by storing it in a
 // two element FIFO. This is necessary as we only know very late in the cycle whether the load/store will succeed (address check,
 // TLB hit mainly). So we better unconditionally allow another request to arrive and store this request in case we need to.
-module lsu_bypass (
+module lsu_bypass import ariane_pkg::*; (
     input  logic      clk_i,
     input  logic      rst_ni,
     input  logic      flush_i,

src/mmu.sv

@@ -14,9 +14,8 @@
 //              address translation unit. SV39 as defined in RISC-V
 //              privilege specification 1.11-WIP
 
-import ariane_pkg::*;
 
-module mmu #(
+module mmu import ariane_pkg::*; #(
     parameter int unsigned INSTR_TLB_ENTRIES     = 4,
     parameter int unsigned DATA_TLB_ENTRIES      = 4,
     parameter int unsigned ASID_WIDTH            = 1,

src/mult.sv

@@ -1,7 +1,6 @@
 
-import ariane_pkg::*;
 
-module mult (
+module mult import ariane_pkg::*; (
     input  logic                     clk_i,
     input  logic                     rst_ni,
     input  logic                     flush_i,

src/multiplier.sv

@@ -14,9 +14,8 @@
 //              This unit relies on retiming features of the synthesizer
 //
 
-import ariane_pkg::*;
 
-module multiplier (
+module multiplier import ariane_pkg::*; (
     input  logic                     clk_i,
     input  logic                     rst_ni,
     input  logic [TRANS_ID_BITS-1:0] trans_id_i,