try to disable riscv toolchain

Jason2866 · Sep 14, 2024 · 8ace397 · 8ace397
1 parent 8cb622d
commit 8ace397
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/platform.py b/platform.py
@@ -145,10 +145,12 @@ def configure_default_packages(self, variables, targets):
                 tc_path = "file://" + join(IDF_TOOLS_PATH_DEFAULT, "tools", "tc-xt-esp32")
                 self.packages["xtensa-esp-elf"]["optional"] = False
                 self.packages["xtensa-esp-elf"]["version"] = tc_path
+                del self.packages["riscv32-esp-elf"]
             else:
                 tc_path = "file://" + join(IDF_TOOLS_PATH_DEFAULT, "tools", "tc-rv32")
                 self.packages["riscv32-esp-elf"]["optional"] = False
                 self.packages["riscv32-esp-elf"]["version"] = tc_path
+                del self.packages["xtensa-esp-elf"]
 
         # Enable FSM ULP toolchain for ESP32, ESP32S2, ESP32S3 when IDF is selected
         for available_mcu in ("esp32", "esp32s2", "esp32s3"):