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1. riscv riscv Public

   Forked from openhwgroup/cv32e40p

   RISCY is an in-order 4-stage RISC-V RV32IMFCXpulp CPU

   SystemVerilog

2. core-v-docs core-v-docs Public

   Forked from openhwgroup/programs

   Documentation for the OpenHW Group's set of CORE-V RISC-V cores

   Python

3. core-v-verif core-v-verif Public

   Forked from openhwgroup/core-v-verif

   Functional verification project for the CORE-V family of RISC-V cores.

   Assembly