Merge 8bac82c into f43342b

Cargo.toml

@@ -34,22 +34,22 @@ exclude = [
 
 [workspace.dependencies]
 # Dependencies from the `fuel-core` repository:
-fuel-core-client = { version = "0.28.0", default-features = false }
-fuel-core-types = { version = "0.28.0", default-features = false }
+fuel-core-client = { version = "0.30.0", default-features = false }
+fuel-core-types = { version = "0.30.0", default-features = false }
 
 # Dependencies from the `fuel-vm` repository:
-fuel-asm = "0.52.0"
-fuel-crypto = "0.52.0"
-fuel-types = "0.52.0"
-fuel-tx = "0.52.0"
-fuel-vm = "0.52.0"
+fuel-asm = "0.54.1"
+fuel-crypto = "0.54.1"
+fuel-types = "0.54.1"
+fuel-tx = "0.54.1"
+fuel-vm = "0.54.1"
 
 # Dependencies from the `fuels-rs` repository:
 fuels-core = "0.64.0"
 fuels-accounts = "0.64.0"
 
 # Dependencies from the `forc-wallet` repository:
-forc-wallet = "0.8.1"
+forc-wallet = { git = "https://github.com/fuelLabs/forc-wallet", branch = "kayagokalp/0.54.1" }
 
 # Dependencies from the `fuel-abi-types` repository:
 fuel-abi-types = "0.5.0"
@@ -61,3 +61,18 @@ homepage = "https://fuel.network/"
 license = "Apache-2.0"
 repository = "https://github.com/FuelLabs/sway"
 
+[patch.crates-io]
+fuels-core = { git = "https://github.com/fuelLabs/fuels-rs", rev = "8735c431b036b932a6663ded26494b51b0b298a9" }
+fuels-accounts = { git = "https://github.com/fuelLabs/fuels-rs", rev = "8735c431b036b932a6663ded26494b51b0b298a9" }
+fuels-programs = { git = "https://github.com/fuelLabs/fuels-rs", rev = "8735c431b036b932a6663ded26494b51b0b298a9" }
+fuels = { git = "https://github.com/fuelLabs/fuels-rs", rev = "8735c431b036b932a6663ded26494b51b0b298a9" }
+
+fuel-asm = { git = "https://github.com/fuelLabs/fuel-vm", branch = "dento/blob-tx" }
+fuel-crypto = { git = "https://github.com/fuelLabs/fuel-vm", branch = "dento/blob-tx" }
+fuel-types = { git = "https://github.com/fuelLabs/fuel-vm", branch = "dento/blob-tx" }
+fuel-tx = { git = "https://github.com/fuelLabs/fuel-vm", branch = "dento/blob-tx" }
+fuel-vm = { git = "https://github.com/fuelLabs/fuel-vm", branch = "dento/blob-tx" }
+
+fuel-core-client = { git = "https://github.com/fuelLabs/fuel-core", branch = "dento/blob-tx" }
+fuel-core-types = { git = "https://github.com/fuelLabs/fuel-core", branch = "dento/blob-tx" }
+fuel-core-storage = { git = "https://github.com/fuelLabs/fuel-core", branch = "dento/blob-tx" }

sway-ast/src/expr/op_code.rs

@@ -259,7 +259,9 @@ define_op_codes!(
     ),
     (Croo, CrooOpcode, "croo", (addr: reg, contract: reg)),
     (Csiz, CsizOpcode, "csiz", (ret: reg, contract: reg)),
-    (Ldc, LdcOpcode, "ldc", (contract: reg, addr: reg, size: reg)),
+    (Bsiz, BsizOpcode, "bsiz", (ret: reg, contract: reg)),
+    (Ldc, LdcOpcode, "ldc", (contract: reg, addr: reg, size: reg, mode: imm)),
+    (Bldd, BlddOpcode, "bldd", (dst_ptr: reg, addr: reg, offset: reg, len: reg)),
     (
         Log,
         LogOpcode,

sway-core/src/asm_generation/finalized_asm.rs

@@ -537,6 +537,8 @@ fn print_instruction(op: &Instruction) {
         Instruction::WDMM(x) => f("WDMM", x.unpack()),
         Instruction::WQMM(x) => f("WQMM", x.unpack()),
         Instruction::ECAL(x) => f("ECAL", x.unpack()),
+        Instruction::BSIZ(x) => f("BSIZ", x.unpack()),
+        Instruction::BLDD(x) => f("BLDD", x.unpack()),
     }
 }
 

sway-core/src/asm_lang/allocated_ops.rs

@@ -180,7 +180,19 @@ pub(crate) enum AllocatedOpcode {
     ),
     CROO(AllocatedRegister, AllocatedRegister),
     CSIZ(AllocatedRegister, AllocatedRegister),
-    LDC(AllocatedRegister, AllocatedRegister, AllocatedRegister),
+    BSIZ(AllocatedRegister, AllocatedRegister),
+    LDC(
+        AllocatedRegister,
+        AllocatedRegister,
+        AllocatedRegister,
+        VirtualImmediate06,
+    ),
+    BLDD(
+        AllocatedRegister,
+        AllocatedRegister,
+        AllocatedRegister,
+        AllocatedRegister,
+    ),
     LOG(
         AllocatedRegister,
         AllocatedRegister,
@@ -330,7 +342,9 @@ impl AllocatedOpcode {
             CCP(_r1, _r2, _r3, _r4) => vec![],
             CROO(_r1, _r2) => vec![],
             CSIZ(r1, _r2) => vec![r1],
-            LDC(_r1, _r2, _r3) => vec![],
+            BSIZ(r1, _r2) => vec![r1],
+            LDC(_r1, _r2, _r3, _i0) => vec![],
+            BLDD(_r1, _r2, _r3, _r4) => vec![],
             LOG(_r1, _r2, _r3, _r4) => vec![],
             LOGD(_r1, _r2, _r3, _r4) => vec![],
             MINT(_r1, _r2) => vec![],
@@ -454,7 +468,9 @@ impl fmt::Display for AllocatedOpcode {
             CCP(a, b, c, d) => write!(fmtr, "ccp  {a} {b} {c} {d}"),
             CROO(a, b) => write!(fmtr, "croo {a} {b}"),
             CSIZ(a, b) => write!(fmtr, "csiz {a} {b}"),
-            LDC(a, b, c) => write!(fmtr, "ldc  {a} {b} {c}"),
+            BSIZ(a, b) => write!(fmtr, "bsiz {a} {b}"),
+            LDC(a, b, c, d) => write!(fmtr, "ldc  {a} {b} {c} {d}"),
+            BLDD(a, b, c, d) => write!(fmtr, "bldd {a} {b} {c} {d}"),
             LOG(a, b, c, d) => write!(fmtr, "log  {a} {b} {c} {d}"),
             LOGD(a, b, c, d) => write!(fmtr, "logd {a} {b} {c} {d}"),
             MINT(a, b) => write!(fmtr, "mint {a} {b}"),
@@ -630,7 +646,13 @@ impl AllocatedOp {
             }
             CROO(a, b) => op::CROO::new(a.to_reg_id(), b.to_reg_id()).into(),
             CSIZ(a, b) => op::CSIZ::new(a.to_reg_id(), b.to_reg_id()).into(),
-            LDC(a, b, c) => op::LDC::new(a.to_reg_id(), b.to_reg_id(), c.to_reg_id()).into(),
+            BSIZ(a, b) => op::BSIZ::new(a.to_reg_id(), b.to_reg_id()).into(),
+            LDC(a, b, c, d) => {
+                op::LDC::new(a.to_reg_id(), b.to_reg_id(), c.to_reg_id(), d.value.into()).into()
+            }
+            BLDD(a, b, c, d) => {
+                op::BLDD::new(a.to_reg_id(), b.to_reg_id(), c.to_reg_id(), d.to_reg_id()).into()
+            }
             LOG(a, b, c, d) => {
                 op::LOG::new(a.to_reg_id(), b.to_reg_id(), c.to_reg_id(), d.to_reg_id()).into()
             }

sway-core/src/asm_lang/mod.rs

@@ -485,10 +485,13 @@ impl Op {
                 let (r1, r2) = two_regs(handler, args, immediate, whole_op_span)?;
                 VirtualOp::CSIZ(r1, r2)
             }
-
+            "bsiz" => {
+                let (r1, r2) = two_regs(handler, args, immediate, whole_op_span)?;
+                VirtualOp::BSIZ(r1, r2)
+            }
             "ldc" => {
-                let (r1, r2, r3) = three_regs(handler, args, immediate, whole_op_span)?;
-                VirtualOp::LDC(r1, r2, r3)
+                let (r1, r2, r3, i0) = three_regs_imm_06(handler, args, immediate, whole_op_span)?;
+                VirtualOp::LDC(r1, r2, r3, i0)
             }
             "log" => {
                 let (r1, r2, r3, r4) = four_regs(handler, args, immediate, whole_op_span)?;
@@ -981,6 +984,65 @@ fn two_regs_imm_12(
     Ok((reg.clone(), reg2.clone(), imm))
 }
 
+fn three_regs_imm_06(
+    handler: &Handler,
+    args: &[VirtualRegister],
+    immediate: &Option<Ident>,
+    whole_op_span: Span,
+) -> Result<
+    (
+        VirtualRegister,
+        VirtualRegister,
+        VirtualRegister,
+        VirtualImmediate06,
+    ),
+    ErrorEmitted,
+> {
+    if args.len() > 3 {
+        handler.emit_err(CompileError::IncorrectNumberOfAsmRegisters {
+            span: whole_op_span.clone(),
+            expected: 3,
+            received: args.len(),
+        });
+    }
+    let (reg, reg2, reg3) = match (args.first(), args.get(1), args.get(2)) {
+        (Some(reg), Some(reg2), Some(reg3)) => (reg, reg2, reg3),
+        _ => {
+            return Err(
+                handler.emit_err(CompileError::IncorrectNumberOfAsmRegisters {
+                    span: whole_op_span,
+                    expected: 3,
+                    received: args.len(),
+                }),
+            );
+        }
+    };
+    let (imm, imm_span): (u64, _) = match immediate {
+        None => {
+            return Err(handler.emit_err(CompileError::MissingImmediate {
+                span: whole_op_span,
+            }));
+        }
+        Some(i) => match i.as_str()[1..].parse() {
+            Ok(o) => (o, i.span()),
+            Err(_) => {
+                return Err(
+                    handler.emit_err(CompileError::InvalidImmediateValue { span: i.span() })
+                );
+            }
+        },
+    };
+
+    let imm = match VirtualImmediate06::new(imm, imm_span) {
+        Ok(o) => o,
+        Err(e) => {
+            return Err(handler.emit_err(e));
+        }
+    };
+
+    Ok((reg.clone(), reg2.clone(), reg3.clone(), imm))
+}
+
 impl fmt::Display for Op {
     fn fmt(&self, fmtr: &mut fmt::Formatter<'_>) -> fmt::Result {
         // We want the comment to always be 40 characters offset to the right to not interfere with
@@ -1073,7 +1135,9 @@ impl fmt::Display for VirtualOp {
             CCP(a, b, c, d) => write!(fmtr, "ccp {a} {b} {c} {d}"),
             CROO(a, b) => write!(fmtr, "croo {a} {b}"),
             CSIZ(a, b) => write!(fmtr, "csiz {a} {b}"),
-            LDC(a, b, c) => write!(fmtr, "ldc {a} {b} {c}"),
+            BSIZ(a, b) => write!(fmtr, "bsiz {a} {b}"),
+            LDC(a, b, c, d) => write!(fmtr, "ldc {a} {b} {c} {d}"),
+            BLDD(a, b, c, d) => write!(fmtr, "bldd {a} {b} {c} {d}"),
             LOG(a, b, c, d) => write!(fmtr, "log {a} {b} {c} {d}"),
             LOGD(a, b, c, d) => write!(fmtr, "logd {a} {b} {c} {d}"),
             MINT(a, b) => write!(fmtr, "mint {a} {b}"),

sway-core/src/asm_lang/virtual_ops.rs

@@ -137,7 +137,19 @@ pub(crate) enum VirtualOp {
     ),
     CROO(VirtualRegister, VirtualRegister),
     CSIZ(VirtualRegister, VirtualRegister),
-    LDC(VirtualRegister, VirtualRegister, VirtualRegister),
+    BSIZ(VirtualRegister, VirtualRegister),
+    LDC(
+        VirtualRegister,
+        VirtualRegister,
+        VirtualRegister,
+        VirtualImmediate06,
+    ),
+    BLDD(
+        VirtualRegister,
+        VirtualRegister,
+        VirtualRegister,
+        VirtualRegister,
+    ),
     LOG(
         VirtualRegister,
         VirtualRegister,
@@ -283,7 +295,9 @@ impl VirtualOp {
             CCP(r1, r2, r3, r4) => vec![r1, r2, r3, r4],
             CROO(r1, r2) => vec![r1, r2],
             CSIZ(r1, r2) => vec![r1, r2],
-            LDC(r1, r2, r3) => vec![r1, r2, r3],
+            BSIZ(r1, r2) => vec![r1, r2],
+            LDC(r1, r2, r3, _i0) => vec![r1, r2, r3],
+            BLDD(r1, r2, r3, r4) => vec![r1, r2, r3, r4],
             LOG(r1, r2, r3, r4) => vec![r1, r2, r3, r4],
             LOGD(r1, r2, r3, r4) => vec![r1, r2, r3, r4],
             MINT(r1, r2) => vec![r1, r2],
@@ -367,6 +381,7 @@ impl VirtualOp {
             |  BAL(_, _, _)
             |  BHEI(_)
             | CSIZ(_, _)
+            | BSIZ(_, _)
             | SRW(_, _, _)
             | TIME(_, _)
             |  GM(_, _)
@@ -406,7 +421,8 @@ impl VirtualOp {
             | CB(_)
             | CCP(_, _, _, _)
             | CROO(_, _)
-            | LDC(_, _, _)
+            | LDC(_, _, _, _)
+            | BLDD(_, _, _, _)
             | LOG(_, _, _, _)
             | LOGD(_, _, _, _)
             | MINT(_, _)
@@ -509,7 +525,9 @@ impl VirtualOp {
             | CCP(_, _, _, _)
             | CROO(_, _)
             | CSIZ(_, _)
-            | LDC(_, _, _)
+            | BSIZ(_, _)
+            | LDC(_, _, _, _)
+            | BLDD(_, _, _, _)
             | LOG(_, _, _, _)
             | LOGD(_, _, _, _)
             | MINT(_, _)
@@ -613,7 +631,9 @@ impl VirtualOp {
             CCP(r1, r2, r3, r4) => vec![r1, r2, r3, r4],
             CROO(r1, r2) => vec![r1, r2],
             CSIZ(_r1, r2) => vec![r2],
-            LDC(r1, r2, r3) => vec![r1, r2, r3],
+            BSIZ(_r1, r2) => vec![r2],
+            LDC(r1, r2, r3, _i0) => vec![r1, r2, r3],
+            BLDD(r1, r2, r3, r4) => vec![r1, r2, r3, r4],
             LOG(r1, r2, r3, r4) => vec![r1, r2, r3, r4],
             LOGD(r1, r2, r3, r4) => vec![r1, r2, r3, r4],
             MINT(r1, r2) => vec![r1, r2],
@@ -730,7 +750,9 @@ impl VirtualOp {
             CCP(_r1, _r2, _r3, _r4) => vec![],
             CROO(_r1, _r2) => vec![],
             CSIZ(r1, _r2) => vec![r1],
-            LDC(_r1, _r2, _r3) => vec![],
+            BSIZ(r1, _r2) => vec![r1],
+            LDC(_r1, _r2, _r3, _i0) => vec![],
+            BLDD(_r1, _r2, _r3, _i0) => vec![],
             LOG(_r1, _r2, _r3, _r4) => vec![],
             LOGD(_r1, _r2, _r3, _r4) => vec![],
             MINT(_r1, _r2) => vec![],
@@ -1073,10 +1095,21 @@ impl VirtualOp {
                 update_reg(reg_to_reg_map, r1),
                 update_reg(reg_to_reg_map, r2),
             ),
-            LDC(r1, r2, r3) => Self::LDC(
+            BSIZ(r1, r2) => Self::BSIZ(
+                update_reg(reg_to_reg_map, r1),
+                update_reg(reg_to_reg_map, r2),
+            ),
+            LDC(r1, r2, r3, i0) => Self::LDC(
+                update_reg(reg_to_reg_map, r1),
+                update_reg(reg_to_reg_map, r2),
+                update_reg(reg_to_reg_map, r3),
+                i0.clone(),
+            ),
+            BLDD(r1, r2, r3, r4) => Self::BLDD(
                 update_reg(reg_to_reg_map, r1),
                 update_reg(reg_to_reg_map, r2),
                 update_reg(reg_to_reg_map, r3),
+                update_reg(reg_to_reg_map, r4),
             ),
             LOG(r1, r2, r3, r4) => Self::LOG(
                 update_reg(reg_to_reg_map, r1),
@@ -1533,10 +1566,20 @@ impl VirtualOp {
             CSIZ(reg1, reg2) => {
                 AllocatedOpcode::CSIZ(map_reg(&mapping, reg1), map_reg(&mapping, reg2))
             }
-            LDC(reg1, reg2, reg3) => AllocatedOpcode::LDC(
+            BSIZ(reg1, reg2) => {
+                AllocatedOpcode::BSIZ(map_reg(&mapping, reg1), map_reg(&mapping, reg2))
+            }
+            LDC(reg1, reg2, reg3, imm0) => AllocatedOpcode::LDC(
+                map_reg(&mapping, reg1),
+                map_reg(&mapping, reg2),
+                map_reg(&mapping, reg3),
+                imm0.clone(),
+            ),
+            BLDD(reg1, reg2, reg3, reg4) => AllocatedOpcode::BLDD(
                 map_reg(&mapping, reg1),
                 map_reg(&mapping, reg2),
                 map_reg(&mapping, reg3),
+                map_reg(&mapping, reg4),
             ),
             LOG(reg1, reg2, reg3, reg4) => AllocatedOpcode::LOG(
                 map_reg(&mapping, reg1),

sway-lib-std/src/execution.sw

@@ -30,3 +30,42 @@ pub fn run_external(load_target: ContractId) -> ! {
     }
     __jmp_mem()
 }
+
+pub fn run_external2(load_target1: ContractId, load_target2: ContractId) -> ! {
+    asm(
+        load_target1: load_target1,
+        load_target2: load_target2,
+        load_target2_heap,
+        heap_alloc_size,
+        length1,
+        length2,
+        ssp_saved,
+        cur_stack_size,
+    ) {
+        // Get lengths of both chunks
+        csiz length1 load_target1;
+        csiz length2 load_target2;
+
+        // Store load_target2 on the heap as it'll be overwritten with the first LDC we do.
+        addi heap_alloc_size zero i32;
+        aloc heap_alloc_size;
+        mcp hp load_target2 heap_alloc_size;
+        move load_target2_heap hp;
+
+        // Save the old $ssp value as that's were the contract will be loaded.
+        move ssp_saved ssp;
+        // Shrink the stack since LDC wants $ssp == $sp
+        sub cur_stack_size sp ssp;
+        cfs cur_stack_size;
+
+        // Do the loads
+        ldc load_target1 zero length1;
+        ldc load_target2_heap zero length2;
+
+        // __jmp_mem jumps to $MEM[$hp], so set that up.
+        addi heap_alloc_size zero i64;
+        aloc heap_alloc_size;
+        sw hp ssp_saved i0;
+    }
+    __jmp_mem()
+}