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Add 7 segment display decoder
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
use ieee.numeric_std.all; | ||
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entity Binary_To_7_Segment_Decoder is | ||
port ( | ||
i_Clk : in std_logic; -- Clock | ||
i_Num : in std_logic_vector(15 downto 0); -- 4 Digit hex number | ||
o_D1, o_D2, o_D3, o_D4 : out std_logic; -- 7 segment display selector | ||
o_A, o_B, o_C, o_D, o_E, o_F, o_G : out std_logic -- 7 segment display segments | ||
); | ||
end Binary_To_7_Segment_Decoder; | ||
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architecture rtl of Binary_To_7_Segment_Decoder is | ||
signal w_First_Digit, w_Second_Digit, w_Third_Digit, w_Fourth_Digit : std_logic_vector(3 downto 0); | ||
signal w_Current_Digit_Content : std_logic_vector(3 downto 0); | ||
signal r_Current_Viewing_Digit : std_logic_vector(1 downto 0) := "00"; | ||
signal w_Output : std_logic_vector(6 downto 0); | ||
begin | ||
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-- Split the number into 4 digits | ||
w_First_Digit <= i_Num(15 downto 12); | ||
w_Second_Digit <= i_Num(11 downto 8); | ||
w_Third_Digit <= i_Num(7 downto 4); | ||
w_Fourth_Digit <= i_Num(3 downto 0); | ||
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-- Selects the current digit to display | ||
w_Current_Digit_Content <= w_First_Digit when r_Current_Viewing_Digit = "00" else | ||
w_Second_Digit when r_Current_Viewing_Digit = "01" else | ||
w_Third_Digit when r_Current_Viewing_Digit = "10" else | ||
w_Fourth_Digit; | ||
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-- Enable the digit to display (active low) | ||
o_D1 <= '0' when r_Current_Viewing_Digit = "00" else | ||
'1'; | ||
o_D2 <= '0' when r_Current_Viewing_Digit = "01" else | ||
'1'; | ||
o_D3 <= '0' when r_Current_Viewing_Digit = "10" else | ||
'1'; | ||
o_D4 <= '0' when r_Current_Viewing_Digit = "11" else | ||
'1'; | ||
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-- 7 segment display decoder | ||
w_Output <= "1111110" when w_Current_Digit_Content = "0000" else -- 0x7E | ||
"0110000" when w_Current_Digit_Content = "0001" else -- 0x30 | ||
"1101101" when w_Current_Digit_Content = "0010" else -- 0x6D | ||
"1111001" when w_Current_Digit_Content = "0011" else -- 0x79 | ||
"0110011" when w_Current_Digit_Content = "0100" else -- 0x33 | ||
"1011011" when w_Current_Digit_Content = "0101" else -- 0x5B | ||
"1011111" when w_Current_Digit_Content = "0110" else -- 0x5F | ||
"1110000" when w_Current_Digit_Content = "0111" else -- 0x70 | ||
"1111111" when w_Current_Digit_Content = "1000" else -- 0x7F | ||
"1111011" when w_Current_Digit_Content = "1001" else -- 0x7B | ||
"1110111" when w_Current_Digit_Content = "1010" else -- 0x77 | ||
"0011111" when w_Current_Digit_Content = "1011" else -- 0x1F | ||
"1001110" when w_Current_Digit_Content = "1100" else -- 0x4E | ||
"0111101" when w_Current_Digit_Content = "1101" else -- 0x3D | ||
"1001111" when w_Current_Digit_Content = "1110" else -- 0x4F | ||
"1000111" when w_Current_Digit_Content = "1111" else -- 0x47 | ||
"0000000"; | ||
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-- 7 segment display output | ||
o_A <= w_Output(6); | ||
o_B <= w_Output(5); | ||
o_C <= w_Output(4); | ||
o_D <= w_Output(3); | ||
o_E <= w_Output(2); | ||
o_F <= w_Output(1); | ||
o_G <= w_Output(0); | ||
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process (i_Clk) | ||
begin | ||
if rising_edge(i_Clk) then | ||
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-- Rotate the digit to display | ||
r_Current_Viewing_Digit <= "01" when r_Current_Viewing_Digit = "00" else | ||
"10" when r_Current_Viewing_Digit = "01" else | ||
"11" when r_Current_Viewing_Digit = "10" else | ||
"00"; | ||
end if; | ||
end process; | ||
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end rtl; |
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library ieee; | ||
use ieee.std_logic_1164.all; | ||
use ieee.numeric_std.all; | ||
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library vunit_lib; | ||
context vunit_lib.vunit_context; | ||
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entity Binary_To_7_Segment_Decoder_TB is | ||
generic (runner_cfg : string); | ||
end entity; | ||
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architecture tb of Binary_To_7_Segment_Decoder_TB is | ||
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signal r_Clk : std_logic := '0'; | ||
signal r_Num : std_logic_vector(15 downto 0) := (others => '0'); | ||
signal w_D1, w_D2, w_D3, w_D4 : std_logic; | ||
signal w_A, w_B, w_C, w_D, w_E, w_F, w_G : std_logic; | ||
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begin | ||
-- Instantiate the UUT | ||
UUT : entity work.Binary_To_7_Segment_Decoder | ||
port map( | ||
i_Clk => r_Clk, -- Clock | ||
i_Num => r_Num, -- 4 Digit hex number | ||
o_D1 => w_D1, o_D2 => w_D2, o_D3 => w_D3, o_D4 => w_D4, -- 7 segment display selector | ||
o_A => w_A, o_B => w_B, o_C => w_C, o_D => w_D, o_E => w_E, o_F => w_F, o_G => w_G -- 7 segment display segments | ||
); | ||
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-- Clock | ||
-- r_Clk <= not r_Clk after 5 ns; | ||
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main : process | ||
begin | ||
test_runner_setup(runner, runner_cfg); | ||
wait for 10 ns; | ||
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r_Num <= x"F1E8"; | ||
wait for 10 ns; | ||
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-- First digit | ||
assert (w_D1 = '0' and w_D2 = '1' and w_D3 = '1' and w_D4 = '1') report "Error: First digit is not the first" severity failure; | ||
assert (w_A = '1' and w_B = '0' and w_C = '0' and w_D = '0' and w_E = '1' and w_F = '1' and w_G = '1') report "Error: First digit display wrong segments" severity failure; | ||
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-- Switch to second digit | ||
r_Clk <= '0'; | ||
wait for 10 ns; | ||
r_ClK <= '1'; | ||
wait for 10 ns; | ||
assert (w_D1 = '1' and w_D2 = '0' and w_D3 = '1' and w_D4 = '1') report "Error: Second digit is not the second" severity failure; | ||
assert (w_A = '0' and w_B = '1' and w_C = '1' and w_D = '0' and w_E = '0' and w_F = '0' and w_G = '0') report "Error: Second digit display wrong segments" severity failure; | ||
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-- Switch to third digit | ||
r_Clk <= '0'; | ||
wait for 10 ns; | ||
r_ClK <= '1'; | ||
wait for 10 ns; | ||
assert (w_D1 = '1' and w_D2 = '1' and w_D3 = '0' and w_D4 = '1') report "Error: Third digit is not the third" severity failure; | ||
assert (w_A = '1' and w_B = '0' and w_C = '0' and w_D = '1' and w_E = '1' and w_F = '1' and w_G = '1') report "Error: Third digit display wrong segments" severity failure; | ||
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-- Switch to fourth digit | ||
r_Clk <= '0'; | ||
wait for 10 ns; | ||
r_ClK <= '1'; | ||
wait for 10 ns; | ||
assert (w_D1 = '1' and w_D2 = '1' and w_D3 = '1' and w_D4 = '0') report "Error: Fourth digit is not the fourth" severity failure; | ||
assert (w_A = '1' and w_B = '1' and w_C = '1' and w_D = '1' and w_E = '1' and w_F = '1' and w_G = '1') report "Error: Fourth digit display wrong segments" severity failure; | ||
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-- Return to first digit | ||
r_Clk <= '0'; | ||
wait for 10 ns; | ||
r_ClK <= '1'; | ||
wait for 10 ns; | ||
assert(w_D1 = '0' and w_D2 = '1' and w_D3 = '1' and w_D4 = '1') report "Error: First digit is not the first" severity failure; | ||
assert(w_A = '1' and w_B = '0' and w_C = '0' and w_D = '0' and w_E = '1' and w_F = '1' and w_G = '1') report "Error: First digit display wrong segments" severity failure; | ||
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-- Switch number without clock | ||
r_Num <= x"1234"; | ||
wait for 10 ns; | ||
assert(w_D1 = '0' and w_D2 = '1' and w_D3 = '1' and w_D4 = '1') report "Error: First digit is not the first" severity failure; | ||
assert(w_A = '0' and w_B = '1' and w_C = '1' and w_D = '0' and w_E = '0' and w_F = '0' and w_G = '0') report "Error: First digit display wrong segments" severity failure; | ||
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wait for 10 ns; | ||
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test_runner_cleanup(runner); -- Simulation ends here | ||
end process; | ||
end architecture; |