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JEDEC DDR Spec, 2005. 64Mb-1Gb (8MB-256MB)

p.5/85 "The purpose of this Standard is to define the minimum set of requirements for JEDEC
compliant 64Mb through 1Gb, X4/X8/X16 DDR SDRAMs."

p.7/85 (Page 1)
"DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION
16 M X4 (4 M X4 X4 banks), 8 M X8 (2 M X8 X4 banks), 4 M X16 (1 M X16 X4 banks)"
Mb or MB? As the spec defines 64Mb-1Gb, It is likely referring to 2MB RAM-64MB sticks) 

"• VDDQ: +2.5 V ±0.2 V for DDR 200, 266, or 333
+2.6 ±0.1 V for DDR 400
• VDD:
+3.3 V ±0.3 V or +2.5 V ±0.2 V for DDR 200, 266,
or 333
+2.6 ±0.1 V for DDR 400"


p.66/85 (Page 60) "TABLE 23: Full Strength Driver Characteristics 
Voltage (V)
Pull-- Down Current (mA)
Pull-- Up Current (mA)
Nominal
Low Nominal
High Minimum Maximum Nominal
Low Nominal
High Minimum Maximum
0.1(V) 6.0 6.8 4.6 9.6 --6.1 --7.6 --4.6 --10.0
0.2    12.2 13.5 9.2 18.2 --12.2 --14.5 --9.2 --20.0"

p.68/85 (Page 62) "100-200mV power consumption
TABLE 24: Weak Driver Characteristics
Pull-- Down Current (mA)
Pull-- Up Current (mA)
Voltage
V
lt
(V) Nominal Low Nominal High Min Max Nominal
Low Nominal
High Min Max
0.1 3.4 3.8 2.6 5 --3.5 --4.3 --2.6 --5
0.2 6.9 7.6 5.2 9.9 --6.9 --8.2 --5.2 --9.9"

https://github.com/opencomputeproject/ODSA-BoW/blob/master/spec/bow_specification/bow_specification.mdk#bowmodes
(line 357-360)
"In all modes, the data must be clocked DDR: 
the chip-to-chip data wire bit rate is double the clock wire frequency.
All BoW interfaces faster than BoW-64 should also be able to support BoW-64.
Supporting rates other than the defined modes is an implementation choice."

Line 972-974:

"All BoW implementations must support signaling based on a 0.75 V "I/O voltage".
BoW PHYs may also support higher or lower signaling 
voltages, but must support 0.75 V based signaling for interoperability. "

Bunch of Wires Implementation idea: set compatibility of DDR to 0.7V, but support underclocking all the way to 0.1V & 0.2V, which, according to p.68/85 (Page 62), consumes as little as 2.6mA (min for pull down current), and 5mA for Max. At Full Strength Driver, 100mV DDR consumes 4.6mA-9.6mA. However, it is unclear whether this is continuously running, and power consumption was likely measured at a higher node- 90nm or even 130nm, not 28nm RAM (a 2005 spec).