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riscv: 把内核编译target改为riscv64gc & 获取time csr的频率 & 修正浮点保存与恢复的汇编的问题 #699

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merged 3 commits into from
Apr 6, 2024
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riscv: 把内核编译target改为riscv64gc & 获取time csr的频率 & 修正浮点保存与恢复的汇编的问题 #699

merged 3 commits into from
Apr 6, 2024

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  1. riscv: 获取time csr的频率
  2. 把内核编译target改为riscv64gc
  3. fix: 修正浮点保存与恢复的汇编的问题

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@fslongjin: no appropriate reviewer found, use r? to override

@dragonosbot dragonosbot added O-riscv64 Target: riscv64 O-x86_64 Target: x86_64 S-等待审查 Status: 等待assignee以及相关方的审查。 T-doc Relevant to the document team, which will review and decide on the PR/issue. T-driver Relevant to the driver team, which will review and decide on the PR/issue. labels Apr 6, 2024
@fslongjin fslongjin merged commit 23ef2b3 into DragonOS-Community:master Apr 6, 2024
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O-riscv64 Target: riscv64 O-x86_64 Target: x86_64 S-等待审查 Status: 等待assignee以及相关方的审查。 T-doc Relevant to the document team, which will review and decide on the PR/issue. T-driver Relevant to the driver team, which will review and decide on the PR/issue.
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@fslongjin @dragonosbot