Serial-Peripheral-Interface

Objective

1. To understand the SPI communication protocol and its advantages like less latency and more throughput over UART and I2C.
2. To implement the logic using Verilog and therefore, establish the SPI communication between 2 FPGA boards.
3. To do waveform analysis and verify the feasibility of the state machine that we have designed.
4. To verify the full-duplex communication i.e. correct data is transmitted and received.

Block Diagram in the top-level

Details about the sub-blocks

1. Master Block:
   • This is the device that initiates the process of communication and controls the data transfer.
   • The master device generates the clock signal and selects the slave device with which it wants to communicate.
   • It typically consists of shift registers for receiving and transmitting data, a clock generator, and a control logic.
2. Slave Block:
   • This is a device that receives and responds to commands initiated by the master device.
   • It listens for the chip select signal from the master and responds with the appropriate data.
   • It typically consists of a shift register and control logic for decoding the control signals from the SPI master. The shift register is used to hold the data that is being transmitted or received, while the control logic is responsible for generating the appropriate control signals for the chip select line and the MISO (Master-In-Slave-Out) and MOSI (Master-Out-Slave-In) lines.
   • This device needs to be synchronized with the master clock signal.
3. Wires:
   • SCLK ( Serial Clock ): Used to synchronize the data transfer between the master and slave devices.
   • CS ( Chip select ): Used to select the slave device with which the master wants to communicate.
   • MOSI ( Master-out, Slave-in ): Used to transmit data from the master to the slave device.
   • MISO ( Master-in, Slave-out ): Used to transmit data from the slave to the master device.
4. Shift registers:
   • These are storage elements that would be storing the received data or the data to be transmitted.
   • We would be implementing the 8-bit registers.
   • The registers would be working according to the FIFO rule i.e. the bit that was stored first would be transmitted first.

Detailed steps of Project implementation

1. Ideation and Brainstorming:
   • Our team began the project by conducting ideation and brainstorming sessions to gain a better understanding of the fundamentals of the SPI protocol, as well as its advantages over other communication protocols.
   • Once we had a clear understanding of the requirements, we proceeded to create a top-level design for our implementation, which included a block diagram to outline the various components and their interactions.
   • To ensure proper functionality, we then designed a finite state machine to govern the behavior of our implementation.
   • This helped to ensure that the various components of our implementation worked together in a coordinated and efficient manner.
   • Overall, this approach helped us to develop a clear roadmap for our project and ensured that we remained focused on the key requirements throughout the implementation process.
2. Implementation
   • During the ideation stage, we developed a comprehensive block diagram and FSM to serve as a roadmap for the logic programming process.
   • Our first step was to design the master module in compliance with all required specifications.
   • We then created a slave module with an identical FSM, but with miso and mosi functionalities reversed to facilitate communication.
   • To enable full duplex communication, we designed a top module that seamlessly connected the master and slave modules.
   • As we were implementing the 4-wire single slave version of the SPI protocol, the master module is responsible for synchronizing a single slave.
3. Testing:
   • Testing is a crucial component of hardware programming, and as such, we allocated significant time to debugging and validating our code.
   • To ensure accuracy at every level, we created testbenches for the sub-blocks and conducted individual tests on the master and slave blocks.
   • Our focus was on verifying one-way communication (half-duplex) between the blocks initially, which proved successful as evidenced by the waveform analysis of the sub-blocks.
   • Subsequently, we proceeded to test the top module, which facilitated the two-way communication.
   • This proved to be the most challenging part of the testing process as most of the checkpoints were internal for the top module. Therefore, debugging took longer than anticipated.
   • Despite the challenges, we remained diligent in our efforts and committed to resolving any issues that arose.

Finite State Machine (FSM)/ Flowchart

Xilinx Simulation Results of sub-blocks

• Master block



• Slave block


• Top-level block

Conclusion

The SPI Master module will accomplish the following:

• Converting 8-bit parallel data received by the host into serial data and transmitting it to the slave.
• Receive serial data from the slave, convert it to parallel data, and output it through the parallel port.
• Output the input signal required by the slave, the clock signal SCLK, and the chip select signal CS.

The SPI Slave module will accomplish the following:

• Receive serial data from the master performing the desired operations based on the commands received.
• Output the input signal required by the master.

References

• https://hackaday.io/project/119133-rops/log/144622-starting-with-verilog-and-spi
• https://www.fpga4fun.com/SPI2.html
• https://fastbitlab.com/spi-behind-scene-data-communication-principle/
• https://www.researchgate.net/publication/339088398_FPGA_Implementation_of_SPI_Bus_Communication_Based_on_State_Machine_Method

Team Members

1. Bhawna Rana
   
2. Jaya Bansal
   
3. Kaashvi Jain
   
4. Vaishnavi Virat Dave