#1779: CI: actually add Intel 19, fix misleading name

DARMA-tasking · May 5, 2022 · 296ee9e · 296ee9e
1 parent f836ecf
commit 296ee9e
Showing 1 changed file with 21 additions and 0 deletions.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -9,6 +9,26 @@ variables:
 
 # before_script:
 
+intel18:
+  variables:
+    OMPI_FC: "ifort"
+    FC: "ifort"
+    OMPI_CC: "icc"
+    CC: "icc"
+    OMPI_CXX: "icpc"
+    CXX: "icpc"
+    SCHEDULER_PARAMETERS: "--account=${ASC_WCID} --partition=short,batch --time=1:00:00 --nodes=1"
+  stage: build
+  script:
+    - source /projects/empire/installs/chama/INTEL-RELEASE-OPENMP-SHARED/trilinos/latest-link/load_matching_env.sh
+    - http_proxy=http://proxy.sandia.gov:80 https_proxy=http://proxy.sandia.gov:80 VT_RDMA_TESTS_ENABLED=0 ci/build_cpp.sh $CI_PROJECT_DIR $CI_PROJECT_DIR/vt_build_intel19
+    - ci/test_cpp.sh $CI_PROJECT_DIR $CI_PROJECT_DIR/vt_build_intel19
+  only:
+    refs:
+      - develop
+  tags:
+    - intel19_usr
+
 intel19:
   variables:
     OMPI_FC: "ifort"
@@ -21,6 +41,7 @@ intel19:
   stage: build
   script:
     - source /projects/empire/installs/chama/INTEL-RELEASE-OPENMP-SHARED/trilinos/latest-link/load_matching_env.sh
+    - module swap intel intel/19
     - http_proxy=http://proxy.sandia.gov:80 https_proxy=http://proxy.sandia.gov:80 VT_RDMA_TESTS_ENABLED=0 ci/build_cpp.sh $CI_PROJECT_DIR $CI_PROJECT_DIR/vt_build_intel19
     - ci/test_cpp.sh $CI_PROJECT_DIR $CI_PROJECT_DIR/vt_build_intel19
   only: