end_condition

Type

object

Default

By default, the simulation stops after the specified number of clock cycles has been completed.

Description

Specifies the condition for terminating the simulation. PROLEAD can stop the simulation when a primary output signal reaches a defined state, such as when a "done" signal is set to logic 1. Alternatively, the simulation can be terminated after a predefined number of clock cycles.

Impact

None; select the option that best suits your design.

Examples

Termination After a Certain Number of Cycles

"simulation": {
    "end_condition": {
        "clock_cycles": 5 
    }
}

In this example, PROLEAD ends the simulation after 5 clock cycles.

Termination via a done Signal

"simulation": {
    "end_condition": {
        "signals": {
            "name": "done",
            "value": "1'b1"
        }
    }
}

In this example, PROLEAD ends the simulation if a signal named done is set to one.