Hardware beginner's guide

Welcome to the beginner's guide to PROLEAD for hardware design evaluation! Whether you're a hardware enthusiast, an engineer, or a designer, PROLEAD is here to assist you in evaluating your own masked hardware designs. With its powerful features and user-friendly interface, PROLEAD aims to simplify the evaluation process and help you maximize the potential of your designs. In this comprehensive guide, we will take you through the essential steps to effectively evaluate your hardware designs using PROLEAD. By the end of this guide, you will have a solid understanding of how to leverage this amazing tool and make the most out of its features.

Installation

Before diving into the evaluation process with PROLEAD, it's important to ensure that you have successfully installed the tool. If you haven't done so already, please refer to Installation for detailed instructions on the installation steps. Once you have PROLEAD up and running, we can begin exploring the step-by-step process of evaluating your masked hardware designs.

Implementation

The first step in evaluating the side-channel security of a masked hardware design is to design the masked hardware circuit itself. You have the flexibility to use any hardware description language of your choice. However, it is essential to ensure that your final design is synthesizable. To help you understand the concept of a masked hardware circuit and provide you with an example to work with, we have provided a masked VHDL implementation of the AES refered to as CMS, byte-serial AES-128. In the following, we focus on this example. For more examples, we refer to our Examples.

Hint: Designing a masked hardware circuit can be a challenging task. However, there is a solution that can simplify the process and ensure provable security. If you are not familiar with hardware masking or want to streamline the construction of masked hardware designs, AGEMA can help you. With AGEMA, all you need to do is provide your hardware design without masking, and the tool takes care of the rest.

Synthesis

As PROLEAD expects a gate-level netlist written in Verilog, the next step in the process is to synthesize the RTL (Register Transfer Level) code of your design. Synthesis is the process of transforming the RTL description into an optimized gate-level representation suitable for evaluation. For a more detailed description of this step, we refer to Synthesis. We recommend to use either the commercial Synopsys Design Compiler or the open-source tool Yosys. For Yosys, we already provide a synthesis script and a custom cell library cell library. To run the script on the RTL code of CMS, byte-serial AES-128, just type:

cd yosys/syn
bash synthesize.sh vhdl ../../examples/Hardware/AES_Enc_CMS_d1/rtl/ aes_top

Evaluation