Fix trailing whitespace

B-Lang-org · Aug 20, 2024 · 9d7921f · 9d7921f
1 parent 0ea992e
commit 9d7921f
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Showing 6 changed files with 7 additions and 7 deletions.
diff --git a/src/Libraries/Base1/Vector.bs b/src/Libraries/Base1/Vector.bs
@@ -1302,7 +1302,7 @@ instance (Add n1 1 n, ConcatTuple' n1 a b, AppendTuple b b c) => ConcatTuple' n
     let v1 :: Vector (TExp n1) a = take v
         v2 :: Vector (TExp n1) a = drop v
     in concatTuple' v1 `appendTuple` concatTuple' v2
-  unconcatTuple' x = 
+  unconcatTuple' x =
     let res :: (b, b) = splitTuple x
         v1 :: Vector (TExp n1) a = unconcatTuple' res.fst
         v2 :: Vector (TExp n1) a = unconcatTuple' res.snd

diff --git a/src/comp/IExpandUtils.hs b/src/comp/IExpandUtils.hs
@@ -2016,7 +2016,7 @@ chkIfcPortNames errh args ifcs (ClockInfo ci co _ _) (ResetInfo ri ro) =
     when (not (null emsgs)) $ bsError errh emsgs
   where
     input_clock_ports i =
-      case lookup i ci of 
+      case lookup i ci of
         Just (Just (VName o, Right (VName g))) -> [o, g]
         Just (Just (VName o, Left _)) -> [o]
         _ -> []
@@ -2041,7 +2041,7 @@ chkIfcPortNames errh args ifcs (ClockInfo ci co _ _) (ResetInfo ri ro) =
 
     default_clock_names = [ (n, idDefaultClock) | n <- input_clock_ports idDefaultClock ]
     default_reset_names = [ (n, idDefaultReset) | n <- input_reset_ports idDefaultReset ]
-    
+
     arg_names = sort $
       arg_port_names ++ arg_inout_names ++ arg_clock_names ++ arg_reset_names ++
       default_clock_names ++ default_reset_names

diff --git a/src/comp/PragmaCheck.hs b/src/comp/PragmaCheck.hs
@@ -557,7 +557,7 @@ checkModulePortNames flgs pos pps vtis ftps =
 
         isClkField (_,t,_) = t == tClock
         isRstField (_,t,_) = t == tReset
-    
+
         (clk_fs, other_fs) = partition isClkField ftps
         (rst_fs, _) = partition isRstField other_fs
 

diff --git a/testsuite/bsc.verilog/splitports/DeepSplit.bs b/testsuite/bsc.verilog/splitports/DeepSplit.bs
@@ -50,7 +50,7 @@ interface SplitTest =
 
 {-# synthesize mkDeepSplitTest #-}
 mkDeepSplitTest :: Module SplitTest
-mkDeepSplitTest = 
+mkDeepSplitTest =
   module
     interface
       putFoo (DeepSplit x) = $display "putFoo: " (cshow x)

diff --git a/testsuite/bsc.verilog/splitports/InstanceSplit.bs b/testsuite/bsc.verilog/splitports/InstanceSplit.bs
@@ -51,7 +51,7 @@ interface SplitTest =
 
 {-# synthesize mkInstanceSplitTest #-}
 mkInstanceSplitTest :: Module SplitTest
-mkInstanceSplitTest = 
+mkInstanceSplitTest =
   module
     interface
       putFoo x = $display "putFoo: " (cshow x)

diff --git a/testsuite/bsc.verilog/splitports/ShallowSplit.bs b/testsuite/bsc.verilog/splitports/ShallowSplit.bs
@@ -34,7 +34,7 @@ interface SplitTest =
 
 {-# synthesize mkShallowSplitTest #-}
 mkShallowSplitTest :: Module SplitTest
-mkShallowSplitTest = 
+mkShallowSplitTest =
   module
     interface
       putFoo (ShallowSplit x) = $display "putFoo: " (cshow x)