Added Libraries/Misc containing files from private BSV_Additional_Libs

Libraries/Makefile

@@ -7,6 +7,7 @@ BUILD_ORDER = \
 	GenC \
 	COBS \
 	VerilogRepr \
+	Misc \
 
 .PHONY: all
 all: install

Libraries/Misc/CreditCounter.bsv

@@ -0,0 +1,66 @@
+// Copyright (c) 2015-2019 Bluespec, Inc., All Rights Reserved
+//
+// SPDX-License-Identifier: BSD-3-Clause
+
+// A "credit counter" which can be incremented and decremented
+// concurrently in the same clock (by using CRegs).
+// Author: Rishiyur S. Nikhil
+
+package CreditCounter;
+
+// ================================================================
+// BSV library imports
+
+import Cur_Cycle :: *;
+
+// ================================================================
+// Interface
+
+interface CreditCounter_IFC #(numeric type w);
+   // Current value of internal count
+   method UInt #(w) value;
+
+   // Increment internal count
+   method Action incr;
+
+   // Decrement internal count
+   method Action decr;
+
+   // Clear internal count to 0
+   method Action clear;
+endinterface
+
+// ================================================================
+// Module implementation
+// Scheduling: value < incr < decr < clear
+
+module mkCreditCounter (CreditCounter_IFC #(w));
+
+   Reg #(UInt #(w)) crg [3] <- mkCReg (3, 0);
+
+   method UInt #(w) value = crg [1];
+
+   method Action incr if (crg [0] != maxBound);
+      if (crg [0] == maxBound) begin
+	 $display ("%0d: ERROR: CreditCounter: overflow", cur_cycle);
+	 $finish (1);    // Assertion failure
+      end
+      crg [0] <= crg [0] + 1;
+   endmethod
+
+   method Action decr () if (crg [1] != 0);
+      if (crg [1] == 0) begin
+	 $display ("%0d: ERROR: CreditCounter: underflow", cur_cycle);
+	 $finish (1);    // Assertion failure
+      end
+      crg [1] <= crg [1] - 1;
+   endmethod
+
+   method Action clear;
+      crg [2] <= 0;
+   endmethod
+endmodule
+
+// ================================================================
+
+endpackage

Libraries/Misc/Cur_Cycle.bsv

@@ -0,0 +1,45 @@
+// Copyright (c) 2013-2024 Bluespec, Inc. All Rights Reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+
+package Cur_Cycle;
+
+// ================================================================
+// A convenience function to return the current cycle number during BSV simulations
+// The if-then-else is because in Verilog our $displays work on the
+// opposide edge (in the middle of the clock).
+
+ActionValue #(Bit #(32)) cur_cycle = actionvalue
+                                        Bit #(32) t <- $stime;
+                                        if (genC)
+                                          return t / 10;
+                                        else
+                                          return (t + 5) / 10;
+                                     endactionvalue;
+
+// ================================================================
+// fa_debug_show_location
+// Shows module hierarchy and current cycle
+
+// Note: each invocation looks like this:
+//     fa_debug_show_location; if (verbosity != 0) $display ("<invocation location>");
+
+// Why not define the function as:
+//     function Action fa_debug_show_location (Integer verbosity, String location_s);
+// and just print the location as part of this function?
+
+// This is a workaround, because there's some bug in Verilog codegen
+// and/or Verilator, where that version core dumps.
+
+function Action fa_debug_show_location (Integer verbosity);
+   action
+      if (verbosity != 0) begin
+	 $display ("    %m");
+	 $write ("    %0d: ", cur_cycle);
+      end
+   endaction
+endfunction
+
+// ================================================================
+
+endpackage

Libraries/Misc/EdgeFIFOFs.bsv

@@ -0,0 +1,120 @@
+// Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+
+// EdgeFIFOFs are 1-element FIFOFs used as generic interfaces by IPs
+// where they connect to interconnect fabrics.  The overall interface
+// is a standard FIFOF interface.  The IP-side is guarded.  The
+// Fabric-side is unguarded, so that it's easy to attach transactors
+// for some particular bus interface such as AXI4-Lite, AHB-Lite, etc.
+
+package EdgeFIFOFs;
+
+// ================================================================
+// BSV library imports
+
+import FIFOF :: *;
+
+// ================================================================
+// FIFOFs for Master IPs.
+// enq (IP-side) is guarded, deq (Fabric-side) is not.
+
+module mkMaster_EdgeFIFOF (FIFOF #(t))
+   provisos (Bits #(t, tsz));
+
+   Integer port_deq   = 0;
+   Integer port_enq   = 1;
+   Integer port_clear = 2;
+
+   Array #(Reg #(Bool)) crg_full   <- mkCReg (3, False);
+   Reg #(t)             rg_payload <- mkRegU;
+
+   // ----------------
+   // Clear
+
+   method Action clear;
+      crg_full [port_clear] <= False;
+   endmethod
+
+   // ----------------
+   // Enq side (IP-side; guarded)
+
+   method Bool notFull ();
+      return (! crg_full [port_enq]);
+   endmethod
+
+   method Action  enq (t x) if (! crg_full [port_enq]);
+      crg_full [port_enq] <= True;
+      rg_payload          <= x;
+   endmethod
+
+   // ----------------
+   // Deq side (Fabric-side; unguarded)
+
+   method Bool notEmpty ();
+      return crg_full [port_deq];
+   endmethod
+
+   method t first ();    // unguarded
+      return rg_payload;
+   endmethod
+
+   method Action deq ();    // unguarded
+      crg_full [port_deq] <= False;
+   endmethod
+
+endmodule
+
+// ================================================================
+// For Slave IPs.
+// enq (Fabric-side) is unguarded, deq (IP-side) is guarded.
+
+module mkSlave_EdgeFIFOF (FIFOF #(t))
+   provisos (Bits #(t, tsz));
+
+   Integer port_deq   = 0;
+   Integer port_enq   = 1;
+   Integer port_clear = 2;
+
+   Array #(Reg #(Bool)) crg_full   <- mkCReg (3, False);
+   Reg #(t)             rg_payload <- mkRegU;
+
+   // ----------------
+   // Clear
+
+   method Action clear;
+      crg_full [port_clear] <= False;
+   endmethod
+
+   // ----------------
+   // Enq side (IP-side; unguarded)
+
+   method Bool notFull ();
+      return (! crg_full [port_enq]);
+   endmethod
+
+   method Action  enq (t x);    // unguarded
+      crg_full [port_enq] <= True;
+      rg_payload          <= x;
+   endmethod
+
+   // ----------------
+   // Deq side (Fabric-side; guarded)
+
+   method Bool notEmpty ();
+      return crg_full [port_deq];
+   endmethod
+
+   method t first () if (crg_full [port_deq]);
+      return rg_payload;
+   endmethod
+
+   method Action deq () if (crg_full [port_deq]);
+      crg_full [port_deq] <= False;
+   endmethod
+
+endmodule
+
+// ================================================================
+
+endpackage