π―
Focusing
Hey, I'm Asmith Pampana (@Asmithcodes) π
I'm a final-year Electronics and Communication Engineering student with a passion for building innovative technology.
-
01:24
(UTC +05:30) - in/asmithpampana
Popular repositories Loading
-
Verilog-Programs
Verilog-Programs PublicA dedicated Verilog HDL practice space focused on designing, simulating, and documenting digital logic circuits using Xilinx Vivado. This repository aims to strengthen HDL fundamentals through cleaβ¦
Verilog
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.