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A7-A11, T2 SoC cpufreq support #439

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@asdfugil asdfugil commented Feb 8, 2025

This adds the tunables required for cpufreq to work properly on A7-A11, T2 SoCs, most prominently a register poke to enable voltage changes when the state is changed, as iBoot leaves the voltage controls disabled.

Some power domains are not referenced by other nodes through clock-gates
or power-gates, so this is needed.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
This is the 64-bit variant of poll32().

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
- A7-A8X uses 3 bits only for pstate, and PS1 mask is GENMASK(24, 22)

- Add tunables, mainly the voltage control register in PMGR (iBoot boots us
with voltage changes seemingly disabled, with obvious disastrous outcome
trying to switch to high P-states)

- Remove writes to offset 0x4xxxx from cluster->base for A7-A11. The range
starting from 0x40000 from cluster->base does not exist in ADT /arm-io/pmgr,
so it probably does not exist for those older chips. This includes the
0x440f8 and ppt-thrtl writes.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
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