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Add support for booting on T8012 (T2) SoC #425

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@asdfugil asdfugil commented Dec 1, 2024

This PR contains the changes required to boot the kernel on T2 per this LKML submission:

https://lore.kernel.org/asahi/20241201161942.36027-1-towinchenmi@gmail.com/T/#t

Overall T2 is similar to A10, and this takes care of the remaining:

  • The ultra-narrow touch bar screen, or no screen at all
  • Some memory channels being unused on some devices
  • Some ADT oddities
  • Takes the memory intended for SSD cache and allow the kernel to use it (If a driver for booting x86 ever end up getting made that memory has to be described anyways)

P.S. T2 Boots on the P-core in Apple Fusion Architecture

@asdfugil asdfugil marked this pull request as draft December 3, 2024 05:18
@asdfugil asdfugil marked this pull request as ready for review December 3, 2024 05:19
@asdfugil asdfugil closed this Jan 29, 2025
@asdfugil asdfugil deleted the for-upstream branch January 29, 2025 20:07
@asdfugil asdfugil restored the for-upstream branch January 29, 2025 20:07
@asdfugil asdfugil reopened this Jan 29, 2025
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Address some peculiarities specific to T2:

- Reserved memory at top is very large, either 512 MB or 1536 MB, and only
lowest 512 MB is for OS use.

- Some ranges in /arm-io/ranges is not aligned to the page size. We align
them ourselves instead.

- On models with a screen, the framebuffer is extremely narrow at 60 pixels
in width, so add a smaller logo.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
- Some devices does not have a display internal or external, do not try to
prepare framebuffer on it.

- On T2, memory after 512 MB is used as the ANS2 cache for the x86 CPU,
since this region is very big, the mem_size_actual correction code
needs to be changed.

- Only half of the memory channels are used on T2 with 1 GB of memory,
and this fact must be learned at runtime because the amount of memory
depends on the storage configuration of the host Mac.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
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asdfugil commented Feb 8, 2025

Changes:

  • Drop description of the SSD cache memory region in FDT setup.

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2 participants