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1. he-soc he-soc Public

   C 31 8

2. can_bus can_bus Public

   VHDL 5 1

3. riscv_nn riscv_nn Public

   SystemVerilog 3 2

4. sdio_vip sdio_vip Public

   sdiovip

   Verilog 2

5. i3c-slave-design i3c-slave-design Public

   Forked from NXP/i3c-slave-design

   MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

   Verilog 1 1

6. pulp pulp Public

   Forked from pulp-platform/pulp

   This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

   SystemVerilog