Debug

tests/conftest.py

@@ -421,8 +421,14 @@ def __init__(self, path):
         if not isdir(path):
             raise IOError("Following path must be a valid directory: %s" % path)
         self._path = path
-        self.image_files = {splitext(file_name)[0].strip('v'):realpath(join(self._path, file_name))
-                                    for file_name in listdir(self._path)}
+        self.image_files = {}
+        for filename in listdir(self._path):
+            bname = splitext(filename)[0]
+            s = search(r'v((\d\.)+\d)', bname)
+            if s:
+                self.image_files[s.group(0)] = realpath(join(self._path, filename))
+            else:
+                self.image_files[bname] = realpath(join(self._path, filename))
         self.hdk_versions = sorted(filter(lambda x: match(r'^\d+', x), self.image_files.keys()))
 
     def get_image_id(self, hdk_version=None):

tests/fpga_drivers/_xilinx_xrt.py

@@ -82,10 +82,10 @@ def _get_driver():
         """
         xrt_path = FpgaDriver.get_xrt_lib()
         if _isfile(_join(xrt_path, "lib/libxrt_aws.so")):
-            print('Loading XRT for AWS target')
+            print('Loading XRT API library for AWS targets')
             fpga_library = _cdll.LoadLibrary(_join(xrt_path, "lib/libxrt_aws.so"))
         elif _isfile(_join(xrt_path, "lib/libxrt_core.so")):
-            print('Loading XRT for common target')
+            print('Loading XRT API library for Xilinx targets')
             fpga_library = _cdll.LoadLibrary(_join(xrt_path, "lib/libxrt_core.so"))
         else:
             raise RuntimeError('Unable to find Xilinx XRT Library')

tests/test_hardware_config.py

@@ -3,8 +3,9 @@
 Test metering and floating behaviors of DRM Library.
 """
 import pytest
+from datetime import datetime
 from os.path import join, dirname, realpath
-import accelize_drm as _accelize_drm
+import accelize_drm as accelize_drm
 import tests.conftest as conftest
 from tests.fpga_drivers import get_driver
 
@@ -39,6 +40,7 @@ def test_vitis_2activator(pytestconfig, conf_json, cred_json, async_handler):
     drm_ctrl_base_addr = pytestconfig.getoption("drm_controller_base_address")
     no_clear_fpga = pytestconfig.getoption("no_clear_fpga")
 
+    # Create driver and program FPGA
     fpga_driver_cls = get_driver(driver_name)
     driver = fpga_driver_cls(
                     fpga_slot_id = slot_id,
@@ -47,9 +49,6 @@ def test_vitis_2activator(pytestconfig, conf_json, cred_json, async_handler):
                     no_clear_fpga = no_clear_fpga
                 )
 
-    # Program FPGA
-    driver.program_fpga()
-
     # Get activators
     base_addr = pytestconfig.getoption("activator_base_address")
     activators = findActivators(driver, base_addr)