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Improve thread scheduling for lockhammer #18

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lucasclucasdo
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@lucasclucasdo lucasclucasdo commented May 14, 2018

Add a core interleave argument to lockhammer which determines the order in which logical core numbers are populated.

Fixes #17

Add an option which controls the order in which logical core numbers
are populated.  Lockhammer currently specializes the order in which
it schedules hardware threads for systems where 2 threads share
cpu resources (same physical core, shared cache, etc).  Since several
configurations exist from unique resources per thread to 4 or more
threads per core add the option to arbitrarily select the interleave
between logical core numbers which share physical resources.

Fixes ARM-software#17

Change-Id: I90a04082750f7ebdc5121294e2a214195896c373
Signed-off-by: Lucas Crowthers <lucasc.qdt@qualcommdatacenter.com>
@geoffreyblake
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Can one of the admins verify this patch?

@lucasclucasdo
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Let's rethink this one since it didn't fix the issue Cavium raised. The interleave option is still useful for other reasons but I'd rather not change the affinity setting unless we have a good reason to do so.

@lucasclucasdo lucasclucasdo force-pushed the lh-threadscheduling branch from aee8ca9 to 12b45f8 Compare May 22, 2018 18:04
@lucasclucasdo
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I have updated this PR to only include the interleave command line option. We can address further thread scheduling issues in subsequent PRs after further experimentation.

@@ -265,7 +278,7 @@ void* hmr(void *ptr)
}
else {
/* Calculate affinity mask for my core and set affinity */
CPU_SET(((mycore >> 1)) + ((ncores >> 1) * (mycore & 1)), &affin_mask);
CPU_SET(((mycore * ncores / ileave) % ncores + (mycore / ileave)), &affin_mask);
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Hi Lucas,
Can you add a comment here about the interleaving assumption is 0 - (numcores / numthreads) is thread 0 on each physical core, (numcores / numthreads) - 2 * (numcores / numthreads) is thread 1 on each core etc?

Add some documentation to the source code which describes the
relationship between threads, physical cores, and logical core
numberings and how the interleave option can be used to select
which will be populated first with increasing core counts.

Change-Id: I5a5eee67a4e3f1579690cd76a93deccbccaf4cfd
Signed-off-by: Lucas Crowthers <lucasc.qdt@qualcommdatacenter.com>
@lucasclucasdo lucasclucasdo force-pushed the lh-threadscheduling branch from 817aba4 to abc16f7 Compare May 22, 2018 19:35
@geoffreyblake geoffreyblake merged commit 2afbe0c into ARM-software:integration May 23, 2018
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2 participants