Gator 9.2.1

build-android.sh

@@ -55,7 +55,7 @@ while getopts ":hn:a:t:g:c:o:l:sdv" arg; do
             cmake_generator="${OPTARG}"
             ;;
         o)
-            build_path="${OPTARGS}"
+            build_path="${OPTARG}"
             ;;
         c)
             cmake_exe="${OPTARG}"

build-linux.sh

@@ -46,7 +46,7 @@ while getopts ":hp:g:c:o:l:sdv" arg; do
             cmake_generator="${OPTARG}"
             ;;
         o)
-            build_path="${OPTARGS}"
+            build_path="${OPTARG}"
             ;;
         c)
             cmake_exe="${OPTARG}"

daemon/ProtocolVersion.h

@@ -3,8 +3,8 @@
 
 /* Define the product release version / protocol version */
 
-// Protocol version Streamline v9.2
-#define PROTOCOL_VERSION 920
+// Protocol version Streamline v9.2.1
+#define PROTOCOL_VERSION 921
 // Differentiates development versions from release code
 #define PROTOCOL_VERSION_DEV_MULTIPLIER 100000
 

daemon/events-Neoverse-N1.xml

@@ -1,4 +1,4 @@
-<!-- Copyright (C) 2019-2023 by Arm Limited. All rights reserved. -->
+<!-- Copyright (C) 2019-2024 by Arm Limited. All rights reserved. -->
 
 <counter_set count="6" name="ARMv8_Neoverse_N1_cnt"/>
 <category counter_set="ARMv8_Neoverse_N1_cnt" name="Neoverse-N1" per_cpu="yes" supports_event_based_sampling="yes">
@@ -108,6 +108,10 @@
     <event event="0x90" title="Instructions (Speculated)" name="Load (Acquire)" description="The counter counts memory-read operations with acquire or acquirepc semantics that are speculatively executed" units="instructions"/>
     <event event="0x91" title="Instructions (Speculated)" name="Store (Release)" description="The counter counts memory-write operations with release semantics that are speculatively executed" units="instructions"/>
     <event event="0xa0" title="L3 Data Cache" name="Access (due to read)" description="As &apos;L3 Data Cache: Access&apos;, but counts only attributable memory-read operations that cause a cache access to at least the Level 3 data or unified cache"/>
+    <event event="0x4000" title="Statistical Profiling" name="Sample Population" description="The counter increments for each operation that might be sampled, whether or not the operation was sampled. Operations that are executed at an Exception level or Security state in which the Statistical Profiling Extension is disabled are not counted."/>
+    <event event="0x4001" title="Statistical Profiling" name="Sample Feed" description="The counter increments each time the sample interval counter reaches zero and is reloaded, and the sample does not collide with the previous sample. Samples that are removed by filtering, or discarded, and not written to the Profiling Buffer are counted."/>
+    <event event="0x4002" title="Statistical Profiling" name="Sample Filtered" description="The counter increments each time that a completed sample record is checked against the filters and not removed. Sample records that are not removed by filtering, but are discarded before being written to the Profiling Buffer because of a Profiling Buffer management event, are counted."/>
+    <event event="0x4003" title="Statistical Profiling" name="Sample Collision" description="The counter increments for each sample record that is taken when the previous sampled operation has not completed generating its sample record"/>
 </category>
 <spe name="Arm Neoverse-N1 Statistical Profiling Extension" id="arm_neoverse_n1_spe_pmu" extends="armv8.2_spe">
     <!-- Define data source packet source types [5.3.5 Data Source packet] -->

daemon/events-Neoverse-V1.xml

@@ -114,11 +114,25 @@
     <event event="0x90" title="Instructions (Speculated)" name="Load (Acquire)" description="The counter counts memory-read operations with acquire or acquirepc semantics that are speculatively executed" units="instructions"/>
     <event event="0x91" title="Instructions (Speculated)" name="Store (Release)" description="The counter counts memory-write operations with release semantics that are speculatively executed" units="instructions"/>
     <event event="0xa0" title="L3 Data Cache" name="Access (due to read)" description="As &apos;L3 Data Cache: Access&apos;, but counts only attributable memory-read operations that cause a cache access to at least the Level 3 data or unified cache"/>
+    <event event="0x4000" title="Statistical Profiling" name="Sample Population" description="The counter increments for each operation that might be sampled, whether or not the operation was sampled. Operations that are executed at an Exception level or Security state in which the Statistical Profiling Extension is disabled are not counted."/>
+    <event event="0x4001" title="Statistical Profiling" name="Sample Feed" description="The counter increments each time the sample interval counter reaches zero and is reloaded, and the sample does not collide with the previous sample. Samples that are removed by filtering, or discarded, and not written to the Profiling Buffer are counted."/>
+    <event event="0x4002" title="Statistical Profiling" name="Sample Filtered" description="The counter increments each time that a completed sample record is checked against the filters and not removed. Sample records that are not removed by filtering, but are discarded before being written to the Profiling Buffer because of a Profiling Buffer management event, are counted."/>
+    <event event="0x4003" title="Statistical Profiling" name="Sample Collision" description="The counter increments for each sample record that is taken when the previous sampled operation has not completed generating its sample record"/>
     <event event="0x4004" title="Cycles" name="AMU Constant Cycles" description="This event is defined identically to &apos;Cycles: AMU Constant Cycles&apos; in the AMUv1 architecture"/>
     <event event="0x4005" title="Stalls (Backend)" name="Memory Stall Cycles" description="This event is defined identically to &apos;Stalls (Backend): Memory Stall Cycles&apos; in the AMUv1 architecture"/>
     <event event="0x4006" title="L1 Instruction Cache" name="Miss (due to long-latency read)" description="The counter counts each access counted by &apos;L1 Instruction Cache: Access&apos; that incurs additional latency because it returns instructions from outside the Level 1 instruction cache. The event indicates to software that the access missed in the Level 1 instruction cache and might have a significant performance impact due to the additional latency, compared to the latency of an access that hits in the Level 1 instruction cache."/>
     <event event="0x4009" title="L2 Data Cache" name="Miss (due to long-latency read)" description="The counter counts each memory read access counted by &apos;L2 Data Cache: Access&apos; that incurs additional latency because it returns data from outside the Level 2 data or unified cache of this PE. The event indicates to software that the access missed in the Level 2 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 2 data or unified cache."/>
     <event event="0x400b" title="L3 Data Cache" name="Miss (due to long-latency read)" description="The counter counts each memory read access counted by &apos;L3 Data Cache: Access&apos; that incurs additional latency because it returns data from outside the Level 3 data or unified cache of this PE. The event indicates to software that the access missed in the Level 3 data or unified cache and might have a significant performance impact compared to the latency of an access that hits in the Level 3 data or unified cache."/>
+    <event event="0x8005" title="Instructions (Speculated)" name="Advanced SIMD" description="The counter counts speculatively executed operations due to Advanced SIMD instructions" units="instructions"/>
+    <event event="0x8006" title="Instructions (Speculated)" name="SVE" description="This event counts speculatively executed operations due to SVE instructions" units="instructions"/>
+    <event event="0x8074" title="Instructions (Speculated)" name="Predicated Operations (SVE)" description="The counter counts speculatively executed SIMD data-processing and load and store operations due to SVE instructions with a Governing predicate operand that determines the Active elements" units="instructions"/>
+    <event event="0x8075" title="Instructions (Speculated)" name="Predicated Operations, No Active Predicates (SVE)" description="The counter counts speculatively executed SIMD data-processing and load and store operations due to SVE instructions with a Governing predicate in which all elements are FALSE" units="instructions"/>
+    <event event="0x8076" title="Instructions (Speculated)" name="Predicated Operations, All Active Predicates (SVE)" description="The counter counts speculatively executed SIMD data-processing and load and store operations due to SVE instructions with a Governing predicate in which all elements are TRUE" units="instructions"/>
+    <event event="0x8077" title="Instructions (Speculated)" name="Predicated Operations, Partially Active Predicates (SVE)" description="The counter counts speculatively executed SIMD data-processing and load and store operations due to SVE instructions with a Governing predicate in which elements are neither all TRUE nor all FALSE" units="instructions"/>
+    <event event="0x80bc" title="Instructions (Speculated)" name="Load, First-fault (SVE)" description="The counter counts speculatively executed memory read operations due to SVE First-fault and Non-fault load instructions" units="instructions"/>
+    <event event="0x80bd" title="Instructions (Speculated)" name="Load, First-fault write 0 to FFR (SVE)" description="The counter counts speculatively executed memory read operations due to SVE First-fault and Non-fault load instructions that write 0 to at least one bit in FFR" units="instructions"/>
+    <event event="0x80c0" title="Instructions (Speculated)" name="Floating Point Elements (SVE)" description="The counter counts speculatively executed operations that would be counted by &apos;Instructions (Speculated): Floating Point (SVE)&apos;, except that it is IMPLEMENTATION DEFINED whether this includes operations due to instructions other than those listed in the Floating-point arithmetic (SVE) category in the Arm® Architecture Reference Manual Supplement, The Scalable Vector Extension (SVE), for Armv8-A. The counter is incremented by (128 ÷ CSIZE) and by twice that amount for operations that would also be counted by &apos;Instructions (Speculated): Floating Point, FMA (SVE)&apos;. See Operation counts for dot-product and multiply-accumulate operations on page D7-2719 for information on counts for, dot product, matrix multiplication, and BFloat16 multiply-accumulate instructions." units="instructions"/>
+    <event event="0x80c1" title="Instructions (Speculated)" name="Floating Point Elements (Floating-point and Advanced SIMD)" description="The counter counts speculatively executed operations that would be counted by &apos;Instructions (Speculated): Floating Point (all)&apos; but not by &apos;Instructions (Speculated): Floating Point (SVE)&apos;, and it is IMPLEMENTATION DEFINED whether this includes operations due to instructions other than those listed in the Floating-point arithmetic (scalar) category and the Floating-point arithmetic (Advanced SIMD) category in Arm® Architecture Reference Manual Supplement, The Scalable Vector Extension (SVE), for Armv8-A. The counter is incremented by the specified number of elements for Advanced SIMD operations or by 1 for scalar operations and by twice those amounts for operations that would also be counted by &apos;Instructions (Speculated): Floating Point, FMA (all)&apos;. See Operation counts for dot-product and multiply-accumulate operations on page D7-2719 for information on counts for dot product, matrix multiplication, and BFloat16 multiply-accumulate instructions." units="instructions"/>
 </category>
 <spe name="Arm Neoverse-V1 Statistical Profiling Extension" id="arm_neoverse_v1_spe_pmu" extends="armv8.3_spe_sve">
     <!-- Define data source packet source types [5.3.5 Data Source packet] -->

daemon/events-Neoverse-V2.xml

@@ -114,6 +114,10 @@
     <event event="0x90" title="Instructions (Speculated)" name="Load (Acquire)" description="The counter counts memory-read operations with acquire or acquirepc semantics that are speculatively executed" units="instructions"/>
     <event event="0x91" title="Instructions (Speculated)" name="Store (Release)" description="The counter counts memory-write operations with release semantics that are speculatively executed" units="instructions"/>
     <event event="0xa0" title="L3 Data Cache" name="Access (due to read)" description="As &apos;L3 Data Cache: Access&apos;, but counts only attributable memory-read operations that cause a cache access to at least the Level 3 data or unified cache"/>
+    <event event="0x4000" title="Statistical Profiling" name="Sample Population" description="The counter counts each operation that might be sampled, whether or not the operation was sampled. Operations that are executed at an Exception level or Security state in which the Statistical Profiling Extension is disabled are not counted."/>
+    <event event="0x4001" title="Statistical Profiling" name="Sample Feed" description="The counter counts each time the sample interval counter reaches zero and is reloaded, and the sample does not collide with the previous sample. Samples that are removed by filtering, or discarded, and not written to the Profiling Buffer are counted."/>
+    <event event="0x4002" title="Statistical Profiling" name="Sample Filtered" description="The counter counts each sample counted by &apos;Statistical Profiling: Sample Feed&apos; that is not removed by filtering. Sample records that are not removed by filtering, but are discarded before being written to the Profiling Buffer because of a Profiling Buffer management event or because Discard mode is implemented and enabled, are counted."/>
+    <event event="0x4003" title="Statistical Profiling" name="Sample Collision" description="The counter counts each time the sample interval counter reaches zero and is reloaded, and the sample collides with the previous sample because the previous sampled operation has not completed generating its sample record"/>
     <event event="0x4004" title="Cycles" name="AMU Constant Cycles" description="Constant frequency cycles"/>
     <event event="0x4005" title="Stalls (Backend)" name="Memory Stall Cycles" description="No operation sent due to the backend and memory stalls"/>
     <event event="0x4006" title="L1 Instruction Cache" name="Miss (due to long-latency read)" description="L1 instruction cache long latency miss"/>

daemon/linux/perf/PerfDriver.cpp

@@ -126,6 +126,7 @@ namespace {
             case metrics::metric_priority_t::ipc:
                 return "Basic";
             case metrics::metric_priority_t::l2:
+            case metrics::metric_priority_t::l2i:
                 return "L2 Cache";
             case metrics::metric_priority_t::l3:
                 return "L3 Cache";

daemon/linux/perf/PerfDriverConfiguration.cpp

@@ -274,13 +274,14 @@ namespace {
         LOG_DEBUG("Determining max events for #%zu", cpuNo);
 
         // Set the affinity to just that CPU so that it is online, and so that there are some events generated by perf
-        std::unique_ptr<cpu_set_t, std::function<void(cpu_set_t *)>> cpuset {CPU_ALLOC(cpu_set_size),
+        std::unique_ptr<cpu_set_t, std::function<void(cpu_set_t *)>> cpuset {CPU_ALLOC(cpuNo + 1),
                                                                              [](cpu_set_t * ptr) { CPU_FREE(ptr); }};
 
         CPU_ZERO_S(cpu_set_size, cpuset.get());
         CPU_SET_S(cpuNo, cpu_set_size, cpuset.get());
 
-        // try and set affinity
+        // try and set affinity to ensure cpuNo is doing some work (and won't read 0 events)
+        // Note: This needs to be restored elsewhere.
         bool affinitySucceeded = false;
         for (unsigned count = 0; count < affine_loop_count && !affinitySucceeded; ++count) {
             if (sched_setaffinity(0, cpu_set_size, cpuset.get()) == 0) {