Riscy Cores

Very much a riscy cores, written in SystemVerilog

⇁ Welcome

This is a collection of cores and chips I've built.

Each project is split in the cores folder, with the testbench and design in the tests and src folders respectively.

Below is a tree structure of the current files:

├── README.md
├── assets
└── cores
    ├── conway        # Conway's Game of Life
    │   ├── src
    │   └── tests
    └── riscy32_single # 32 Bit Single Cycle RISC-V Cpu
        ├── src
        └── tests

⇁ Riscy 32 single

Single cycle 32 bit RISC-V CPU. Plan is to use this as a base to make a pipelined 64 bit CPU.

Then I have plans to combine this with a DSP for machine learning.

⇁ Conway's game of life

In case anyone searches how to implement this in SystemVerilog, below is a gif of my Conway's game of life attempt. Note I couldn't make it as square as I wanted it to be, its a bit vertical. And idk why 0,0 is rendered. This is stuff I will investigate later.