llvm: code generation for non-FPU targets looks a bit hairy

[davidgm94]

Zig Version

0.11.0-dev.3322+82632aff2

Steps to Reproduce and Observed Behavior

Related: #12227

When implementing #15938 @N00byEdge and I noticed some weirdness in the code. I don't have enough experience in the compiler to dare to touch these non-trivial bits, but I think someone should. This has been somewhat problematic for the last years of Zig development, virtually stopping some non-FPU targets to compile because of LLVM crashes.

Some of it here:

zig/src/codegen/llvm.zig

Lines 2820 to 2826 in 9461ed5

	.Float => switch (t.floatBits(target)) {
	16 => return if (backendSupportsF16(target)) dg.context.halfType() else dg.context.intType(16),
	32 => return dg.context.floatType(),
	64 => return dg.context.doubleType(),
	80 => return if (backendSupportsF80(target)) dg.context.x86FP80Type() else dg.context.intType(80),
	128 => return dg.context.fp128Type(),
	else => unreachable,

zig/src/codegen/llvm.zig

Lines 11145 to 11150 in 9461ed5

	fn backendSupportsF80(target: std.Target) bool {
	return switch (target.cpu.arch) {
	.x86_64, .x86 => !std.Target.x86.featureSetHas(target.cpu.features, .soft_float),
	else => false,
	};
	}

zig/src/codegen/llvm.zig

Lines 11155 to 11170 in 9461ed5

	fn backendSupportsF16(target: std.Target) bool {
	return switch (target.cpu.arch) {
	.powerpc,
	.powerpcle,
	.powerpc64,
	.powerpc64le,
	.wasm32,
	.wasm64,
	.mips,
	.mipsel,
	.mips64,
	.mips64el,
	=> false,
	else => true,
	};
	}

zig/src/codegen/llvm.zig

Lines 11175 to 11180 in 9461ed5

	fn backendSupportsF128(target: std.Target) bool {
	return switch (target.cpu.arch) {
	.amdgcn => false,
	else => true,
	};
	}

Expected Behavior

Some unification should happen in my opinion for this aspect of the code generation to avoid bugs and crashes.

[alexrp]

Is there something concrete you'd like to see changed/improved in this code?

The cases where we avoid emitting certain float types like half, fp128, etc have to do with working around LLVM backend crashes or miscompilations.