From f092ad99c95728d6177a250f471eb28b3f145979 Mon Sep 17 00:00:00 2001 From: azaidy Date: Wed, 8 Nov 2023 16:15:23 +0000 Subject: [PATCH 1/2] Display statements are removed during synthesis --- utils/rtl/tl2umi_np.v | 8 ++++++++ utils/rtl/umi2tl_np.v | 18 +++++++++++++++--- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/utils/rtl/tl2umi_np.v b/utils/rtl/tl2umi_np.v index 0f7d5353..ed07bfe6 100644 --- a/utils/rtl/tl2umi_np.v +++ b/utils/rtl/tl2umi_np.v @@ -317,10 +317,12 @@ module tl2umi_np #( tl_d_source <= dataag_out_resp_source; put_bytes_resp <= dataag_out_resp_bytes; end + `ifndef SYNTHESIS else begin // Not supported request, ignore $display("Unsupported response on UMI side %d", dataag_out_resp_cmd_opcode); end + `endif end end RESP_RD_BRST: begin @@ -381,8 +383,10 @@ module tl2umi_np #( end end default: begin + `ifndef SYNTHESIS // Entered wrong state $display("Entered Invalid State in Response State Machine"); + `endif end endcase @@ -628,8 +632,10 @@ module tl2umi_np #( endcase end default: begin + `ifndef SYNTHESIS // Not supported request, ignore $display("Unsupported request on TL side %d", tl_a_opcode); + `endif end endcase end @@ -693,8 +699,10 @@ module tl2umi_np #( end end default: begin + `ifndef SYNTHESIS // Entered wrong state $display("Entered Invalid State in Request State Machine"); + `endif end endcase diff --git a/utils/rtl/umi2tl_np.v b/utils/rtl/umi2tl_np.v index 2fad1704..a9228410 100644 --- a/utils/rtl/umi2tl_np.v +++ b/utils/rtl/umi2tl_np.v @@ -270,7 +270,11 @@ module umi2tl_np #( tl_a_opcode_r <= `TL_OP_LogicalData; end end - default: $display("[UMI2TL]: Unsupported UMI Request"); + default: begin + `ifndef SYNTHESIS + $display("[UMI2TL]: Unsupported UMI Request"); + `endif + end endcase end end @@ -293,7 +297,11 @@ module umi2tl_np #( UMI_REQ_ATOMICMAXU: tl_a_param_r <= `TL_PA_MAXU; UMI_REQ_ATOMICMINU: tl_a_param_r <= `TL_PA_MINU; UMI_REQ_ATOMICSWAP: tl_a_param_r <= `TL_PL_SWAP; - default: $display("[UMI2TL]: Unsupported UMI Atomic"); + default: begin + `ifndef SYNTHESIS + $display("[UMI2TL]: Unsupported UMI Atomic"); + `endif + end endcase end else begin @@ -458,7 +466,11 @@ module umi2tl_np #( case (tl_d_opcode) `TL_OP_AccessAck: udev_resp_cmd_opcode_r <= UMI_RESP_WRITE; `TL_OP_AccessAckData: udev_resp_cmd_opcode_r <= UMI_RESP_READ; - default: $display("[UMI2TL]: Unsupported TileLink Response"); + default: begin + `ifndef SYNTHESIS + $display("[UMI2TL]: Unsupported TileLink Response"); + `endif + end endcase end end From 130ac10284853170742f18f9757883af6f3fd654 Mon Sep 17 00:00:00 2001 From: azaidy Date: Wed, 8 Nov 2023 19:56:52 +0000 Subject: [PATCH 2/2] Redirect to stable state from default case --- utils/rtl/tl2umi_np.v | 62 ++++++++++++++++++++++++++++++++++++++----- utils/rtl/umi2tl_np.v | 12 ++++----- 2 files changed, 61 insertions(+), 13 deletions(-) diff --git a/utils/rtl/tl2umi_np.v b/utils/rtl/tl2umi_np.v index ed07bfe6..471b3e91 100644 --- a/utils/rtl/tl2umi_np.v +++ b/utils/rtl/tl2umi_np.v @@ -317,12 +317,22 @@ module tl2umi_np #( tl_d_source <= dataag_out_resp_source; put_bytes_resp <= dataag_out_resp_bytes; end - `ifndef SYNTHESIS else begin - // Not supported request, ignore + // Not supported response type. Ignore and stay in idle. + resp_state <= RESP_IDLE; + dataag_out_resp_ready_assert <= 1'b1; + tl_d_valid <= 1'b0; + tl_d_opcode <= 3'b0; + tl_d_size <= 3'b0; + tl_d_source <= 5'b0; + tl_d_data <= 64'b0; + put_ack_resp <= 1'b0; + put_bytes_resp <= 8'b0; + get_ack_resp <= 1'b0; + `ifndef SYNTHESIS $display("Unsupported response on UMI side %d", dataag_out_resp_cmd_opcode); + `endif end - `endif end end RESP_RD_BRST: begin @@ -383,8 +393,18 @@ module tl2umi_np #( end end default: begin + // Entered wrong state. Return to idle. + resp_state <= RESP_IDLE; + dataag_out_resp_ready_assert <= 1'b1; + tl_d_valid <= 1'b0; + tl_d_opcode <= 3'b0; + tl_d_size <= 3'b0; + tl_d_source <= 5'b0; + tl_d_data <= 64'b0; + put_ack_resp <= 1'b0; + put_bytes_resp <= 8'b0; + get_ack_resp <= 1'b0; `ifndef SYNTHESIS - // Entered wrong state $display("Entered Invalid State in Response State Machine"); `endif end @@ -530,7 +550,7 @@ module tl2umi_np #( always @(posedge clk or negedge nreset) begin if (~nreset) begin - req_state <= 'b0; + req_state <= REQ_IDLE; tl_a_ready_assert <= 1'b1; uhost_req_packet_cmd_opcode <= 'b0; uhost_req_packet_cmd_len <= 'b0; @@ -542,6 +562,7 @@ module tl2umi_np #( uhost_req_packet_data <= 'b0; uhost_req_packet_valid_r <= 1'b0; ml_tx_non_zero_mask_r <= 1'b0; + put_ack_req <= 1'b0; put_bytes_req <= 8'b0; end else begin @@ -632,8 +653,21 @@ module tl2umi_np #( endcase end default: begin + // Not supported request type. Ignore and stay in idle. + req_state <= REQ_IDLE; + tl_a_ready_assert <= 1'b1; + uhost_req_packet_cmd_opcode <= 'b0; + uhost_req_packet_cmd_len <= 'b0; + uhost_req_packet_cmd_size <= 'b0; + uhost_req_packet_cmd_atype <= 'b0; + uhost_req_packet_cmd_eom <= 'b0; + uhost_req_packet_dstaddr <= 'b0; + uhost_req_packet_srcaddr <= 'b0; + uhost_req_packet_data <= 'b0; + uhost_req_packet_valid_r <= 1'b0; + ml_tx_non_zero_mask_r <= 1'b0; + put_bytes_req <= 8'b0; `ifndef SYNTHESIS - // Not supported request, ignore $display("Unsupported request on TL side %d", tl_a_opcode); `endif end @@ -699,8 +733,22 @@ module tl2umi_np #( end end default: begin + // Entered wrong state. Return to idle. + req_state <= REQ_IDLE; + tl_a_ready_assert <= 1'b1; + uhost_req_packet_cmd_opcode <= 'b0; + uhost_req_packet_cmd_len <= 'b0; + uhost_req_packet_cmd_size <= 'b0; + uhost_req_packet_cmd_atype <= 'b0; + uhost_req_packet_cmd_eom <= 'b0; + uhost_req_packet_dstaddr <= 'b0; + uhost_req_packet_srcaddr <= 'b0; + uhost_req_packet_data <= 'b0; + uhost_req_packet_valid_r <= 1'b0; + ml_tx_non_zero_mask_r <= 1'b0; + put_ack_req <= 1'b0; + put_bytes_req <= 8'b0; `ifndef SYNTHESIS - // Entered wrong state $display("Entered Invalid State in Request State Machine"); `endif end diff --git a/utils/rtl/umi2tl_np.v b/utils/rtl/umi2tl_np.v index a9228410..d874ceb4 100644 --- a/utils/rtl/umi2tl_np.v +++ b/utils/rtl/umi2tl_np.v @@ -270,11 +270,11 @@ module umi2tl_np #( tl_a_opcode_r <= `TL_OP_LogicalData; end end + `ifndef SYNTHESIS default: begin - `ifndef SYNTHESIS $display("[UMI2TL]: Unsupported UMI Request"); - `endif end + `endif endcase end end @@ -297,11 +297,11 @@ module umi2tl_np #( UMI_REQ_ATOMICMAXU: tl_a_param_r <= `TL_PA_MAXU; UMI_REQ_ATOMICMINU: tl_a_param_r <= `TL_PA_MINU; UMI_REQ_ATOMICSWAP: tl_a_param_r <= `TL_PL_SWAP; + `ifndef SYNTHESIS default: begin - `ifndef SYNTHESIS $display("[UMI2TL]: Unsupported UMI Atomic"); - `endif end + `endif endcase end else begin @@ -466,11 +466,11 @@ module umi2tl_np #( case (tl_d_opcode) `TL_OP_AccessAck: udev_resp_cmd_opcode_r <= UMI_RESP_WRITE; `TL_OP_AccessAckData: udev_resp_cmd_opcode_r <= UMI_RESP_READ; + `ifndef SYNTHESIS default: begin - `ifndef SYNTHESIS $display("[UMI2TL]: Unsupported TileLink Response"); - `endif end + `endif endcase end end